Operating voltages for digital systems have dropped from 5 V to 3 V or lower, because of the demand for higher-speed logic families that use ICs with smaller geometries. Contributing to the drop as well are the low power-consumption requirements of mobile wireless devices, such as cellular phones, handheld computers, and GPS receivers.
Today, there are many 3-V logic families available. (Note that the term 3 V is commonly used when the supply voltage is 3.3 V). In many designs, however, 3-V systems coexist with legacy 5-V systems, and both supply voltages are mixed on the same circuit board. With the introduction of even lower voltage standards, such as 2.5 V and 1.8 V, it can be expected that mixed voltage interfacing issues will be around for many years.
There are pitfalls to watch out for when interfacing mixed-voltage systems. These pitfalls can be avoided by paying close attention to a few key issues. These include the maximum voltages applied to the input and output pins, the current flowing between the power supplies, and the input-switching threshold levels that must be met.
Although this article addresses interfacing logic ICs in 5-V and 3-V systems that use TTL and CMOS switching levels, the concepts discussed can be applied to interfacing other voltage levels as well. Understanding these concepts will help you to avoid the pitfalls and allow you to design circuits with reliable data transfer between the 5-V and 3-V systems.
Some circuits have limitations on the voltage that can be applied to an input or output pin. These circuits can have current paths to VCC through diodes or parasitic elements. If the voltage is high enough, current will flow into the device to the 3-V supply. If connected to a 5-V signal, you will have the 5-V supply charging the 3-V supply. Excessive current can also damage the diodes and circuitry.
In the suspend or power-down modes, when the 3-V supply drops to 0 V, large currents can flow to ground, or an active-HIGH bus can be pulled down to ground. Either of these situations will cause data disruption and may damage components. The important thing to bear in mind is to not allow current to flow to VCC while it's active at 3 V or while it's at 0 V in a suspend mode.
Also, it's important to remember that there are different scenarios for having 5-V components drive 3-V components and vice versa. A mixture of TTL and CMOS switching levels can exist too. The driver must meet the receiver's input switching level with enough margin and do it without damaging the circuitry. These issues become apparent after examining some I/O circuits in detail.
Virtually all the inputs of a digital circuit will contain an electrostatic discharge (ESD) protection circuit. This circuit is present between the physical input pin and the active circuit.
The classic CMOS scheme provides protection against negative zaps by the diodes to ground (Fig. 1a). Positive zaps are clamped by the diode connected to VCC. The disadvantage of such a circuit is that its maximum input voltage is limited to VCC + 0.5 V to keep current from flowing to the supply. With a VCC of 3 V, the allowed input voltage is too low for direct interfacing to most 5-V systems. Most 5-V systems apply at least 3.6 V to the input.
Some low-voltage circuits may still use two ESD diodes connected to ground. Instead of a third diode, they may use a double transistor circuit (Fig. 1b). Two transistors, bipolar or MOS, act as fast Zener diodes protecting against zaps. The diode connected to VCC is removed, and the maximum input voltage isn't limited by VCC.
Typically, such circuits have a breakdown voltage between 7 V and 10 V, easily allowing input voltages from any 5-V system. The 3-V families that have 5-V tolerant inputs are LVC, LVT, ALVT, LCX, LVX, LPT, and FCT3. Plus, Philips ALVC devices without bus-hold inputs also are 5-V tolerant.
Devices using bus-hold circuits are the LVC, ALVC, LVT, VCX, and ALVT families. A bus-hold circuit has a small MOS transistor acting as a pullup or pulldown device to hold the input at the last valid logic level after the input is left floating.
The circuit in Figure 2a provides an example of a bus-hold circuit for an LVC device. The upper PMOS transistor has an intrinsic parasitic diode that's usually connected between the source and drain, creating a current path to VCC. The comparator shorts out the diode when the input voltage is 0.5 V higher than VCC. This eliminates the current path and makes the input 5-V tolerant.
Figure 2b is an example of a bus-hold circuit for LVT and ALVT devices. This implementation uses a series Schottky blocking diode so that there's no current path to VCC, making the input 5-V tolerant.
Manufacturers of ICs implement the bus-hold circuits into their 3-V LVC, LVT, and ALVT families in different ways. Still, they are all 5-V tolerant. On the other hand, the 3-V ALVC and VCX devices don't have protection circuitry, so their input voltage is limited to VCC +0.5V.
A simplified version of a CMOS output circuit for 3-V CMOS devices is shown in Figure 3. When the output voltage exceeds VCC by more than a diode drop, the intrinsic diode of the upper PMOS transistor forms a current path from the output to VCC. This circuit needs protection circuitry to make it 5-V tolerant.
In one LVC output device implementation with protection circuitry, the comparator shorts out the diode when the output rises above VCC, thereby eliminating the current path (Fig. 4). This makes the output 5-V tolerant, but only in the three-state mode.
During suspend mode when VCC is 0 V, the comparator shorts the diode and protects the circuit. In the active-HIGH state, current can still flow to VCC through the upper PMOS transistor during a HIGH bus-contention situation. Because the transistor is a unipolar device, current will flow from the drain to the source when the drain voltage is higher than the source voltage.
Figure 5 shows a less-complex representation of a biCMOS output for LVT and ALVT devices. These families use tandem bipolar and CMOS transistors to achieve high output drive with rail-to-rail output voltage swings. Current won't flow back to VCC through the upper npn bipolar transistor. To simplify the illustration, the intrinsic diode is not shown in the upper PMOS transistor. Potentially, however, it creates a current path from the output to VCC.
Protection circuitry is used in LVT and ALVT outputs, where the output shares a bus with a 5-V driver (Fig. 6). Again, to simplify the illustration, the bipolar transistors aren't shown. A back-biased Schottky diode prevents current from flowing from the output to VCC. This protects the circuit while it's in the three-state mode. In the active-HIGH mode, the comparator shuts off the upper PMOS transistor if a HIGH contention condition is present when both drivers are driving the bus. During suspend mode with the 3-V supply at 0 V, the comparator and Schottky diode protect the output.
Furthermore, LPT and LCX are two more 3-V families that have 5-V tolerant outputs. All of the 3-V logic families discussed in this section use some form of output protection to achieve 5-V tolerance. Although component manufacturers may implement the output protection differently, all are 5-V tolerant in at least the three-state and suspend modes.
The 3-V families offering the protection even during HIGH bus-contention conditions provide the most flexibility for 5-V interfacing. In order to determine the interfacing capability that each family has to offer, review the manufacturer's data sheets and application notes.
Because the 3-V part getting driven is often a transceiver, the "input" is effectively an input paralleled by an output. This means that the behavior of an output also is important when its voltage exceeds VCC. For this type of device, both input and output circuit considerations must be evaluated together.
To ensure reliable data exchange in mixed voltage systems, input switching levels must be met, and input voltage ratings must not be exceeded.
Use Figure 7 as an example. TTL levels are 2.0 V for VIH and 0.8 V for VIL. CMOS levels are 0.7 × VCC for VIH and 0.3 × VCC for VIL. For systems with a VCC of 5 V ±0.5 V, the CMOS inputs will require 3.85 V at minimum for VIH and 1.35 V at maximum for VIL.
Four signal-level configurations have to be addressed in mixed 3-V/5-V design. One is 5-V TTL outputs driving 3-V TTL inputs. Another is 3-V outputs driving 5-V TTL inputs. The last configurations are 5-V CMOS outputs driving 3-V TTL inputs, and 3-V outputs driving 5-V CMOS inputs:
- Usually, 5-V TTL devices can drive 3-V TTL inputs because the typical bipolar output structures don't have the full output voltage swing. When a 5-V output is HIGH, internal voltage drops limit the output voltage, which is typically VCC −2VBE. That's about 3.6 V. This will often work without causing current to flow from the 5-V supply to the 3-V supply. But, because driver structures can vary, as a precaution, you should check the output voltage capability of the driver.
- Without any difficulty, 3-V devices can drive 5-V TTL inputs. Whether they are CMOS or biCMOS, the 3-V outputs can deliver practically the full output voltage swing of 3 V. The 2-V logic-HIGH threshold level required for 5-V TTL inputs is easily met.
- You must choose carefully when using 5-V CMOS devices to drive 3-V TTL inputs. Select 3-V receivers that are 5-V tolerant, like the families described by the previous sections on 3-V input circuits.
- While it was mentioned earlier that 3-V outputs can drive 5-V TTL inputs, be aware that the situation is quite different for 5-V CMOS inputs. Take note that 3-V outputs won't reliably drive 5-V CMOS inputs. Earlier, we stated that with a worst case 5-V VCC of 5.5 V, the minimum required VIH is 3.85 V, which the 3-V output won't deliver.
A reliable way to drive 5-V CMOS inputs is to use a special dual-VCC level shifter. Many vendors offer dual-VCC level shifter devices with separate power-supply pins for each side of the device. The 3-V half interfaces to 3-V systems, and the 5-V half interfaces to 5-V systems. A common part type is a 74XXX4245 function, which is similar to the generic 74XXX245 transceiver, but has two supply pins instead of one (Fig. 8).
Level shifting in the 74LVC4245 device is done internally. Plus, the dual-supply voltages ensure that each port will have rail-to-rail output-voltage swings with good noise margins. This makes the part ideal for driving 5-V CMOS inputs. The disadvantage is that the addition of a 5-V power supply will increase power consumption.
A simple solution, such as the 74XXX07 function, uses an open-drain buffer to drive 5-V CMOS inputs. The 74LVC07 device has open drain outputs that are 5-V tolerant and can be connected to the 5-V supply through a pullup resistor (Fig. 9).
Legacy 5-V systems continue to coexist with 3-V and lower voltage systems. This means that the need to interface mixed-voltage systems will be around for the foreseeable future. There are pitfalls to look out for when designing these systems. The key to avoiding these pitfalls is to understand and apply the basic concepts discussed here. By doing so, you ensure that the circuits you design will have reliable data transfer between the different voltages.