Electronic Design

Verification Environment Helps With FPGA/SoC Prototypes

Verification has become the bane of the ASIC designer's existence. It consumes from 30% to as much as 70% of total design time. And no one wants to blow $500,000 or more on a mask set that proves worthless.

One answer to the problem is FPGA prototyping, a route that's facilitated by Mentor Graphics' SpeedGate DSV verification environment. Using off-the-shelf Xilinx Virtex FPGAs, designers can create silicon ASIC prototypes and test them at speeds comparable to a real-time operating environment.

The environment addresses everything from hardware partitioning, debugging, and interconnection to rapid board creation and analysis. From the environment's cockpit, users can import any HDL code and visualize their designs as block diagrams or interconnect tables. They can browse through the design's hierarchy in a setting that supports team design, complete with version management to track any changes to the source code. The tool automatically warns users of nonsynthesizable code and isolates it.

Process-level granularity eases partitioning. It enables the moving of individual processes within a module to another FPGA, instead of moving entire modules. Also, automatic insertion of I/O reduction logic in the form of user-defined time-division multiplexing helps with effective use of FPGA I/O pins. Assigning multiple signals to a single pin minimizes the number of needed I/Os, and thus the number of overall FPGAs.

The environment supports all third-party prototyping boards, including fixed-routed and reconfigurable types. It supports partitioning of designs across multiple boards as well as creation of custom boards with links to most major pc-board layout tools. Available now for $98,500 for a floating license, it supports Sun Solaris 2.7 and 2.8 platforms and is applicable to ASIC partitioning on Xilinx Virtex FPGAs.

Mentor Graphics Corp., www.mentor.com/speedgatedsv; (503) 685-7000.

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