Electronic Design

Virtex-5-Based ASIC Prototyping System Has Total Recall

Based on Xilinx’s Virtex-5 LX330 FPGAs, which are the largest FPGAs available today, the HAPS-50 series ASIC prototyping boards from Hardi Electronics can be stacked or interconnected to handle ASIC designs of virtually any size. The first member in the HAPS-50 family, the HAPS-52, has a capacity of 4 million ASIC gates. More boards in the series will be available within two months.

The HAPS-52 board sports more I/O and inter-FPGA connections than previous generations of the HAPS system. It also offers a global bus, more I/O-voltage regions, and a more flexible clocking scheme. In addition, new functions provide improved monitoring and self-test, as well as remote configuration and setup of the board. Everything possible is made to reduce the time it takes to get the ASIC design running on this FPGA board.

In addition to the hardware improvements in the HAPS-50 series, Hardi has partnered with Synplicity to create a complete verification system. The combination of the HAPS-50 hardware and Synplicity’s Certify software with Total Recall debug technology makes for not only a powerful ASIC verification environment, but also a complete design flow that includes partitioning, synthesis, place and route, and debug.

The HAPS-50 series of motherboards is fully compatible with all previous generations, including the HAPS-10, HAPS-20, and HAPS-30 families. In addition, it meets the HapsTrak standard, which guarantees that all Hardi standard daughterboards and all custom-built boards will fit on the new system.

The HAPS-52 board will be available for delivery to customers in April for $47,000.

Hardi Electronics


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