Electronic Design

Waiting On The Arrival Of Little Green Packages

There's no relief for packaging technology: End-users and OEMs are demanding cost-effective solutions that satisfy space constraints and reliability issues. These solutions also should bring products to market faster than methods that try to place everything on one chip, such as the system on a chip (SoC).

These challenges are coming from all corners of the electronics industry-consumer electronics, communications, automotive, medical, and industrial applications. They're the primary driving force behind the surging popularity of the system-in-a-package (SiP) approach (see "SiP Really Packs It In," electronic design, Nov. 29, 2004, p. 46).

Much of the trend in SiP technology uses existing production equipment and materials to try to stack chips, dies, packages, modules, and other components on top of each other. This enables packages to take advantage of the third dimension (height), instead of just chip length and width. Also, this makes for products with lower costs and faster turnaround, as well as enhanced reliability and performance.

More and more passive components are being squeezed into smaller low-profile packages like chip-scale packages (CSPs) and ball-grid arrays (BGAs), saving some serious space. Their shorter lead lengths contribute to improved performance due to lower parasitic inductances, equivalent series resistances (ESRs), and stray capacitance effects. Discrete-component arrays also are seeing more use than individual components. This in turn lowers packaging costs (fewer component placements) in the assembly process. As pc boards get denser with interconnected components and IC chips, interconnecting wires and copper traces contribute to more crosstalk and noise. Thus, a novel means of interconnecting different chips becomes ever-more crucial.

Under a project funded by the Defense Advanced Research Projects Agency (DARPA), Sun Microsystems is proposing to use "proximity communication" between chips that will permit hundreds of chips to interface with each other in a checkerboard face-to-face arrangement using capacitive coupling (Fig. 1).

The technique, still in the experimental stage, won't be available for at least a few more years. One huge challenge is to ensure that the tiny contacts in adjacent devices are lined up perfectly, because misalignment could compromise signal strength by reducing the coupling area and increasing crosstalk levels.

Moreover, shrinking components and their packages makes for new challenges in heat management. "Thermal performance is always a big challenge," explains Jay Heinick, director of business development for the Discrete Business Unit of Toshiba America Electronic Components.

One way to reduce heating effects is to design the die that's within the package for minimal heat dissipation. With power devices like MOSFETs, Toshiba focuses on lower FET drain-source on-resistance (RDS(ON)), which the company reduced to a few milliohms. The firm has pioneered efforts to develop extremely small packages for small-signal, logic, RF, and power applications like the VESM, fSM, and fS6 packages (Fig. 2).

Materials And Hardware Upgrades
Higher heat levels have prompted developers to improve materials for these packages. Quantum Leap Packaging's patented liquid-crystal material can handle the heat better than conventional plastics and ceramics. Its low-cost, injection-molded, liquid-crystal polymer (LCP) is designed for high-temperature critical applications that require MIL-STD hermeticity levels, as in RF power, medical, automotive, and optical applications.

The firm's most recent LCP formulation, LCPh, withstands 4008C temperatures and is three times as tough as conventional LCPs. Such achievements are due to its low dielectric constant, slow out-gassing, and low moisture absorption, while maintaining extreme tolerances. Best of all, it can be tailored to specific requirements. For instance, the degree and direction of the material's coefficient of thermal expansion can be very tightly controlled.

Heatsinks help reduce package power-dissipation levels by going the high-tech route with micro-electromechanical-system (MEMS) technology. One such MEMS-based heat exchanger is the self-contained microfluidic electrokinetic pump system from Cooligy Inc. This device can cool the latest microprocessors, which consume over 100 W. Reactive NanoTechnologies came up with a platform-joining technology for heatsink monitoring that reduces interface thermal resistance tenfold. The metallic-bond product fits between a package and a heatsink.

Even the venerable connector is shrinking. Nano-miniature connectors with center-to-center contact spacings of 0.025 in. (instead of 0.05 in. for D-style connectors) are making the rounds. Like D connectors, they meet MIL-STD-83513 requirements and can handle up to 1 A per contact line.

Get The Lead Out
Environmentally friendly electronics that are free from toxic materials like lead, mercury, bromine, and halogen has become a top-of-the-list issue in packaging. This movement is particularly strong in Europe and Japan, and it's gaining momentum in the U.S. Other harmful electronics materials include cadmium, hexavalent chromium, polybrominated diphenyl ethers (PBDEs), polybrominated biphenyls (PBBs), antimony, and phosphorous.

The green trend is driving the development of less harmful materials. Lead already has been purged from water pipes, gasoline, paints, food packing, and cans, so why can't it be taken out of electronics, too? Steps toward lead-free electronics include the Waste Electrical and Electronic Equipment (WEEE) and the Restriction on the use of certain Hazardous Substances (RoHS) acts adopted by the European Parliament, which will take effect August 13, 2005 and July 1, 2006, respectively.

According to Nokia, there's a strong demand in the consumer sector for lead-free products. The company says that 76% of consumers prefer environmentally safe products if the end product's price and quality matches what they purchase now. Plus, 44% of consumers purchase lead-free electronics because they're environmentally safe. In fact, Nokia points out that 40% of lead formed in landfills in the U.S. comes from consumer electronic products. The consumer sector has shown significant market growth in the use of SiP packages, one of the fastest-growing packaging options (Fig. 3).

Worldwide, most companies offer the choice of lead-free products. Some don't have an option beyond lead-free. The focus is on developing new die-attach adhesives, encapsulants, and molding compounds, solders, leadframes, and material finishes. Most SiP technologies already are based on lead-free assembly processes and are qualified to moisture sensitivity level (MSL) III 2508C reflow soldering conditions.

IBM recently signed an agreement with Suss MicroTec, a supplier of production equipment for semiconductor processing, including MEMS ICs. Suss MicroTec will develop a complete line of 200- and 300-mm wafer equipment to enable commercialization of IBM's C4NP (Controlled Collapse Chip Connect New Process). The C4NP is the first 100% lead-free, flip-chip technology to offer high reliability, fine pitch, lower material costs, and the flexibility to use virtually all types of solder compositions.

Challenges remain in becoming totally lead-free in electronics. Lead-free solder alloys that include various combinations of tin, copper, silver, bismuth, and zinc are under investigation, as are pc-board finishes using combinations of these elements and palladium. Lead frames and component leads also are being finished with some of these elements.

Results have been somewhat mixed so far, but they've been more positive than negative. One study by a Motorola lead-free team showed that some lead-free solder compounds didn't fare as well as those with lead. Another challenge involves using lead-free solders that can work in the surface-mount processing environments of 2458C to 2608C without any pc-board delaminations.

"Tin whiskers" represent a big lead-free challenge when using tin over copper packaging. These whiskers grow on semiconductor packages after the packages go through a lead-free assembly process on a circuit board, where tin is used in place of lead for metal plating. Agere developed a solution by placing a nickel layer between the tin and copper layers.

The lead-free issue is part of a larger scenario for better packaging materials. According to the National Electronics Manufacturers Initiative (NEMI) roadmap, dramatic improvements in materials properties will be necessary. High frequency, high power density, and increased mechanical stress demands must be addressed to support expected future demands (Fig. 4).

Packaging Tech Trends
Smaller And Lower-Profile Packages
The squeeze is on for smaller and lower-profile packages, driven largely by end-user applications in consumer, medical, automotive, and industrial electronics.

SiP Technology Forges Ahead
SiP is proving cost-effective in satisfying many consumer electronics applications. It offers lower-profile, lower-cost, and faster turnaround advantages over other packaging approaches.

Heat Dissipation Headaches
With packages shrinking, heat-dissipation problems are taking on a new urgency. EDA tools are being used increasingly to help resolve this issue.

Better Packaging Materials And Hardware
Improvements in packaging materials and hardware like heatsinks and connectors keep pace with electronic package miniaturization trends.

Eco-Friendly And Safe Packaging
Environmentally friendly and safe lead-free electronics packaging has become a worldwide cause. So are efforts to rid electronics of other hazardous elements that pollute the environment.

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