More functionality in less space is a simple summary of Moore’s Law. What is not so simple is how that Law’s objectives continue to be met by research engineers within the electronics industry. However, a fresh endeavour that directly relates to Moore’s Law has just been announced by two French organisations.
Substrates specialist The Soitec Group and the microelectronics and nanotechnology research centre CEA-Leti are to extend their collaborative work on wafer-to-wafer 3D integration. The two partners plan to offer customers a joint solution that begins with process customization for prototype demonstration and will include licensing 200 and 300-mm technologies.
Soitec’s contribution to the partnership will include its Smart Stacking technology, which enables wafer-to-wafer-level stacking of partially or fully processed circuits, its low-temperature Smart Cut process, and the copper-to-copper bonding technology already in development with CEA-Leti.
CEA-Leti will also offer broad and deep 3D wafer-to-wafer technology and expertise. These include the necessary process steps for different 3D approaches, such as connecting vias, and cost-effective technologies such as wafer pre-processing, bonding, thinning and TSV etching and filling, and post-processing wafer assembly.
All that sounds pretty good but let’s take a deeper look into what this will provide electronic designers. From a footprint perspective, more functionality will be able fit into a smaller space which in turn will allow the development of new generations of smaller, more powerful devices.
But it’s not just about size. There will be benefits in processing speeds. Connections between stacked ICs are shorter and because propagation delay relates to wire length, an increase in speed will result. Shorter wires also provide operational advantages when it comes using less power. They generate less parasitic capacitance. In addition, the reduced power consumption helps to restrict heat generation and contributes to a number of operational advantages relative to the end product in which the 3D ICs will be used. Extended battery life is a prime example.
Bandwidth challenges get some support from stacked chip technology. The way in which the devices are integrated provides an opportunity for a large amount of vias to connect through the layers, which in turns allows the development of more capable bandwidth buses between the stacked layers.
A final and particularly important design benefit of 3D IC integration is a flexibility where it could prove possible to combine components that were previously classified as operationally incompatible in one device.
So Moore’s Law keeps rolling on and although presently some industry experts feel that 3D integration is more suitable for larger rather than small design projects, the stacking principle is definitely moving in the right direction.