Interview: Harry Luan Addresses SoC Design Challenges

Interview: Harry Luan Addresses SoC Design Challenges

Harry Luan, Kilopass’ chief technology officer and vice president of R&D, has been a key member of the Kilopass team since its inception in 2002. He is an expert in CMOS/non-volatile memory (NVM) device physics, modeling, optimization and characterization for technology development, yield enhancement and failure analysis.

Writing in the Journal of VLSI Signal Processing Systems, authors Yen-Kuang Chen and S. Y. Kung, in their article, “Trend and Challenge on System-on-a-Chip Designs,” made the following observation. “By using existing and high-performance IP, SoC designers not only can save time and resources, but also can create a mind-blowing solution that users want… Furthermore, to sell silicon in today’s business environment, semiconductor companies must minimize risk and shorten time-to-market for their customers.” 

According to Harry, as process geometries continue to shrink to 28-nm now and 20-nm and below coming soon, system-on-chip (SoC) designs are increasing in size. This is creating increased demand for intellectual property (IP), especially since memory can comprise more than 50 percent of anSoC’s silicon area. Harry’s looked closely at the challenges facing SoC designers and how IP vendors are helping to overcome some of them.

Wong: What hurdles face SoC designers developing chips at 28-nm and below?

Luan: One problem is finding the intellectual property blocks to fill these large designs. I can only speak for non-volatile memory IP, but our experience will be typical of other IP vendors. Ideally, the SoC design team wants silicon-proven IP at the process node the design is targeting. Additionally, in this world of tight silicon supply at advanced process nodes, the design team will want to be able to take the design to more than one foundry. Thus, having an IP block that is fully qualified at multiple foundries for each process node is a real plus.


Wong: Any IP vendor can claim to be qualified at a particular foundry. What is the metric a designer evaluating IP would expect an IP vendor to meet to back up his claim?

Luan: For suppliers that provide hard IP –– that is, blocks sold as layout or GDSII files –– the benchmark to meet is the JEDEC qualification standard, but it applies to even soft IP sold in the form of RTL code. For example, ARM fabricating its Cortex-A15 MPCore Processor on the TSMC 20nm process node.

The process involves testing packaged units containing the IP fabricated on three different process lots. The qualification process tests the units under accelerated conditions to simulated actual use for an expected product lifetime. The actual types of stress vary depending upon the particular IP. An IP vendor claims qualified products if these qualification results meet pre-defined acceptance criteria. A designer should ask for the actual qualification reports when a prospective vendor is being evaluated. Most often, the foundries can also provide IP qualification status and certifications.


Wong: What types of stress are used to emulate 10 years of life?

Luan: The JEDEC spec call for high temperature operating life (HTOL) and high temperature storage life (HTSL) tests. For our IP, the HTOL qualification tests perform a read operation while the chip is subjected to an elevated supply voltage and subjected to a temperature of 125 degrees Celsius. The HTSL test bakes the chip at 150 degrees Celsius unbiased for 1000 hours.  During the bake, the NVM memory contents are read at 0, 168, 500, and 1000 hours to confirm data retention. In addition, electrostatic discharge (ESD) and latch up (LU)are also tested to meet JESD22.


Wong: How does an IP vendor go about getting a foundry to place their IP blocks on a shuttle run?

Luan: There are two ways. The IP vendor can purchase space on a wafer or the IP can be incorporated on a wafer that his or her IP vendor’s customer has already paid the foundry to fabricate. The foundry benefits in both cases as the IP supply chain will have another qualified IP block SoC designers can select from. The customer benefits from the knowledge that the IP is being qualified if it hadn’t already been silicon proven. And, the IP vendor benefits from having another silicon-proven block to sell to customers.


Wong: How much time is involved from the start of the process to its conclusion?

Luan: Assuming foundry shuttles are available when required, the process takes between nine and 12 months to complete from tapeout to packaged die to first-lot, second-lot, and third-lot qualification. The three lots are staged through the fab at least one week apart from each other.


Wong: What does JEDEC qualification buy the SoC designer?

Luan: Statistical assurance that the IP will work reliably in actual use for the expected product life.

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