DRAM means cheap, standardized memory. We need lots of DRAM to feed our faster processors and ever-expanding network infrastructure and devices. Unfortunately, cheap memory usually means a standard DRAM form accepted by the industry. And that's not going to be. DRAMs are fragmenting into competing architectures—RDRAM, DDR SDRAM, FCRAM, and RLDRAM (see the table).
Moreover, the DRAM application market is fragmenting as well. The DRAM world, with its single-minded standard that we've known and built on, is ending. There will no longer be a single dominant PC-based DRAM architecture. Instead, designers can choose from multiple DRAM architectures. But with that flexibility will come the end of the era of really cheap DRAM. A fragmented market will make it difficult for DRAM vendors to ratchet up production to reach commodity-level pricing. DRAMs now include:
- SDRAM—Synchronous DRAM. Current mainstream SDRAMs clock at 133 MHz, with some at 167 MHz.
- DDR SDRAM—Double Data Rate SDRAM, which clocks data on both clock edges.
- DRDRAM—Direct Rambus DRAM, which uses a high-speed, narrow memory bus and packetized commands, with controllers on both the memory and host sides.
- FCRAM—Fast Cycle SDRAM, which speeds up the access cycle and cuts power.
- RLDRAM—Reduced Latency SDRAM, which reduces access latency and power.
In its glory days, PC-based DRAM had over 70% of the DRAM market. Today, it's a bit above 50% and falling as other markets take larger shares. For example, the share of telecom/datacom servers is growing and will perhaps equal PCs in four or five years. Other applications, like Internet devices, portables, PDAs, and multi-use PCS phones, are building in DRAMs, expanding their market share. Games too have proved a good DRAM base: each Sony Playstation2 has 32 Mbytes of RDRAM.
On the PC front, the battle is between DDR SDRAM and RDRAM. Both deliver high-bandwidth performance: RDRAM over a narrow, high-speed channel, and DDR SDRAM over a wide memory bus. It's too early to project a winner, although RDRAM has an early edge. Intel's 850 chip set for the emerging Pentium 4 has a two-channel RDRAM controller.
However, Intel competitor AMD can't be discounted. AMD has made benchmark hay, beating out the Pentium 4 with its Athalon CPU and 760 chip set teamed with DDR SDRAM. Complicating matters, Intel has moderated its commitment to RDRAM with a new PIV chip set for DDR SDRAM and SDRAM, due out late this year or early next. Additionally, DDR chip sets are emerging from other vendors. In graphics memories, though, DDR seems to be winning hands down.
Server vendors are building on PC133 SDRAM and the emerging PC167 for their wide-access buses. But they're also starting a slow shift to DDR SDRAM, which supports wide-bus implementations. Telecom applications are already accommodating DDR for wide-bus implementations. Yet newer, faster-access FCRAM and RLDRAM also seem to be making inroads into new designs. Both work from the DDR SDRAM interface, so they don't present any major redesign problems.
For the low end of the DRAM market, such as portables, lower power has been a must. New DRAMs, low-power SDRAMs, FCRAMs, and RLDRAMs are on the way to fill that need.
DDR SDRAM is evolutionary, an extension of the current DRAM standards. Simply put, DDR is SDRAM clocked twice, delivering twice the memory bandwidth. Currently, DDR SDRAM supports 100- and 133-MHz versions. Coming is a 167-MHz version. All deliver burst data at twice the clock rate, or from 200 to 333 Mbits/s per pin.
DDR-II, the next generation, is already under development. It will move DDR clock rates to 200 to 400 MHz, delivering 400 to 800 Mbits/s per pin. For a standard 64-bit bus, DDR delivers 1.6- to 2.7-Gbyte/s burst rates. DDR-II will pump this up to 3.2 to 6.4 Gbytes/s.
DDR SDRAM clocks in data from the memory bus twice in a single clock, at twice the clock rate. Yet internally, in its core memory array, it accesses at the input clock rate an array that's twice as wide. It brings in or writes two words per clock. But those operations are done in a single, double-word Read or Write.
It supports burst operations with bursts that are two, four, or eight cycles long. The design includes standard Auto Refresh and Self Refresh modes. Reads and Writes are burst-oriented, starting at an addressed location and counting up in address for a programmed number of cycles. Auto precharge kicks in at the end of a burst access. It hides row precharge and its activation time.
The other major contender for PC DRAM is Rambus' Direct RDRAM. It currently runs a 400-MHz clock (800-MHz edges). A 533-MHz upgrade is available. With an 18-bit channel, it delivers a 1.6- to 2.13-Mbyte/s burst bandwidth per channel. A 600-MHz (1200-MHz edges) version is on the way.
Rambus also is working on a new multilevel voltage strobing scheme that lets each incoming data line carry two bits worth of data values (each voltage level represents a specific dual bit code). This tactic doubles bus bandwidth. Today, the chips support 128 or 144 Mbits, but bit densities are scheduled to rise to 1.2 Gbits in 2003.
DRDRAM comes in 2-by-16d and 16d configurations, with 16 or 32 on-chip memory banks. These memory banks give RDRAM a long burst capability. The banks share sense amps (one per bank). To cut costs, however, Rambus is developing a 4 I version that reduces the on-chip memory banks to 4, with dedicated sense amps. The 4 I is due out next year.
Actually, DRDRAM is more than just another DRAM architecture. It's part of an ongoing revolution: the replacement of parallel system buses. There will probably be no new 32/64-bit, multidrop, parallel buses. Instead, systems are shifting to high-speed, serial or pseudoserial buses and switch fabrics (pseudoserial buses + crossbars).
With its packetized commands and high-speed pseudoserial connections, DRDRAM represents the future. But many wonder if this is an appropriate technology for today.
Developed in the early 1990s and released in 1992, RDRAM is not a classic multidrop, control-signal memory bus. Rather, it relies on command packets sent on a separate 8-bit control bus. It uses high-speed differential clocks that run at multiples of standard memory-bus speeds.
The bus interface is pipelined. The command packets can be clocked in as previous transactions run. This bus logic supports up to eight concurrent transactions in a memory chip.
It isn't a classic memory system where the memory elements are addressed concurrently on the bus and can concurrently respond. Instead, like a card on a multidrop bus, at most only one RDRAM component on the bus will respond to the memory-bus access request. Like boards, it does this by address. For wider buses, designers must add multiple DRDRAM channels (or buses).
To support its high-speed data rates, the memory interface—host side controller, bus signal/data lines, memory controller—is fully specified. These systems need a DRDRAM controller on the chip set and memory side. The intervening signal traces must meet Rambus specifications and require eight layers. This fully defined chip-to-chip interface has proved a mixed blessing. It supports higher clock rates, but it's unpopular with designers who want to do their own memory layout.
DRDRAM is a pipelined architecture, with a fairly deep pipeline of eight stages. It takes eight clocks to load a command packet, but these are fast clocks that are clocked on both edges. With a 400-MHz RDRAM (800-MHz strobe), this packet load will take 10 ns. Overall latency is therefore 10 ns, plus the 45 ns (tRAC) to read the first word, or 55 ns. Moreover, up to 12 ns can be added to this for latencies across the RDRAM bus.
A PC's deeply pipelined, long cache line memory loads aren't optimal for many applications. Instead, applications such as telecom servers, switches, and routers need fast random memory access. For many, there's little locality of reference in their programs or data accesses. Newer DRAM architectures have emerged to meet these requirements. One is the Reduced Latency DRAM (RLDRAM) developed by Infineon.
RLDRAM delivers a low-latency, fast-cycle DRAM. Announced in May, RLDRAM delivers a 25-ns (Read) access time. With a 300-MHz clock and the DDR SDRAM interface, it supports a 2.4-Gbyte/s bandwidth (sustained, cyclic) for an 8-Mbit by 32-bit RLDRAM chip. This rate doubles for a 64-bit interface (two chips wide).
RLDRAM builds on the DDR SDRAM interface. Infineon's designers eliminated the "RAS, then CAS" addressing cycles, however, clocking in the full address into the chip in a single edge. This step helps speed up the access cycle and reduce latency. At 300 MHz, the RLDRAM latency is 22.9 ns for any random address. In contrast, PC133's latency is 43.5 ns (Fig. 1).
The initial RLDRAM memory chips, the 8-Mbit by 32-bit and 16-Mbit by 16-bit, have eight and 16 memory banks, respectively. These RLDRAMs use these banks for cyclic addressing, switching to the next bank for long bursts. This fast cyclic addressing pays the read latency penalty once, for the first access. The following burst accesses do not. The first access takes roughly five clocks.
RLDRAMs were designed for low-power operation with a core 1.8 V. They additionally come in a thin-profile ball-grid-array package with 144 balls. The package provides a low thermal resistance for heat transfer to the pc board or ambient air. It also reduces signal parasitics for high-speed operation.
Another contender for the non-PC DRAM arena is FCRAM. Jointly developed by Fujitsu and Toshiba, FCRAM is a superset of the DDR JEDEC standard. It delivers a 25-ns Read/Write cycle that's about twice as fast as SDRAM (Fig. 2). And, it does it with lower power consumption.
Currently, FCRAM is available in 256-Mbit configurations, with 200- and 154-MHz speed grades. The chips are organized into 16-Mbit by 16-bit or 32-Mbit by 8-bit configurations, each with four on-chip banks. The chips come in a 66-pin, low-cost TSOP (II) package.
Using four of these chips, designers can build a 64-bit wide, 200-MHz memory system with a burst bandwidth of 3.2 Gbytes/s. Wider system buses can up the collective bandwidth. But this bus expansion will need careful design and the use of registered memory modules to minimize skew. FCRAM builds on the standard DRAM core cells.
FCRAM gets fast cycles from a high-speed implementation of the RAS and CAS cycles. The address is latched in 16 bits at a time. The overall access cycles are further reduced with an internal precharge, which does not slow the basic access cycle.
Additionally, FCRAM cuts power by reducing wordline activation power. Only the addressed word is activated. The rest of the words in the line are not. The autoprecharge also is tuned to reduce power. The memory chips use a 2.5-V core voltage to further reduce power consumption. Overall, the FCRAM reduces power dissipation to less than 50% of that of a comparable SDRAM.
A special version of FCRAM has been configured by Fujitsu for mobile phone and portable applications. This memory chip family, the MB82D01171A, provides an SRAM interface and low power dissipation. It's organized as a 16-Mbit by 16-bit memory, with a 90-ns Read cycle time. Maximum currents are limited to 20 mA for active current, 200/100/70 µA for standby, and 10 µA for power-down. The operating voltage is 2.3 to 2.7 V or 2.7 to 3.1 V. The chip comes in a 48-pin plastic FPGA package.
DRAM architectures come and go. What happens to embedded and telecom applications that still need outmoded DRAM parts for deployed products? Not to worry. Integrated Silicon Systems Inc., a fabless memory vendor, has a solution. It builds outmoded DRAM chips on modern fabs, providing pin compatibility with lower power dissipation for chips that currently range from 4- to 64-Mbit DRAMs, as well as SDRAMs.
|Representative DRAM Vendors|
Elpidia Memory Japan
Systems Inc. (ISSI)
(408) 544-4000 www.usa.
Toshiba America Electronics