Flash memory is on a roll. It has gone from a backup, secondary technology to a mainstream product technology that's critical to a wide range of consumer and embedded applications. Flash memory, warts and all, is a key component in most design toolboxes, and it will remain so for at least five years.
The good news is that flash memory will be able to track the silicon curve, at least for the foreseeable future. It will scale, continuing to drop in price per bit, while reaching higher densities for storage applications. Flash is now made on CMOS processes employing features as small as 0.15 to 0.18 µm. Over the next few years, features will scale down to well below 0.1 µm. That will let flash memory manufacturers fabricate chips with capacities exceeding 1 Gbit. Moreover, technologies like the multilevel cell (MLC) structures now pack 2 data bits/flash-memory cell. Further developments promise to bump that up to 3 bits or beyond.
But in the long run, flash may have problems. For one thing, it requires a high 9- to 20-V internal voltage for erasure and programming, and that needs to scale down over time (there is re-search aimed at a 5-V version). In addition, new technologies are emerging that may, with today's silicon and materials technology, provide a better nonvolatile storage medium, as well as eliminate many of flash memory's irregularities, such as nonsymmetric Read/Write and the high-voltage erase/programming. These emerging technologies include:
- FRAM—ferro-electric RAM
- MRAM—mag-netorestive RAM
- OUM—Ovonyx unified memory
- PFRAM—poly-meric ferroelectric RAM
Flash memory is an evolutionary technology, a des-cendant of EPROM and EEPROM. Both are nonvolatile memories, differing in that EPROM is erased by UV light and then electrically programmed, while EEPROM is erased and programmed electrically at the byte level. Like EEPROM, flash is electrically erased and programmed. But it also streamlines the chip design and thus brings down the cost of the overall chip by structuring the memory array to be erased and programmed in a large block rather than byte by byte. By eliminating the control lines to each cell, the storage array can be made smaller. So, the overall chip area of a flash memory is smaller than that of a byte-alterable EEPROM. Engineers, then, get the advantage of cost-effective nonvolatile storage, but they pay for it by having nonsymmetric Read/Write, with a complex, time-consuming Write procedure.
Flash comes in two architectural flavors, usually referred to as NAND and NOR. Basically, NAND-based cells can be viewed as a vertical string of transistors that form a logical NAND gate and share the sense amplifier and control circuitry. NAND-based cells are typically employed in word-serial storage architectures, while NOR structures are employed in memories that have standard random-access interfaces. In contrast, NOR can be viewed as a horizontal string of transistors connected to ground, which forms a basic NOR gate, each with its own sense amplifier and control circuits. Consequently, the basic NOR cell tends to be faster, but it uses more space, while NAND tends to be slower but much smaller (shared sense amplifiers are slower but make for a smaller circuit).
Today, NOR flash dominates, taking up approximately 75% of the market. It's in cell phones, PDAs, set-top boxes, cable modems, and telecom applications. But that NAND/NOR mix is changing, especially for storing digital, video, and audio data. NAND flash typically targets these storage applications, which generally don't need Read speed, but require density. Such applications include mass storage, video and audio storage, and portable storage.
To serve them, NAND flash chips can be had with storage capabilities of 128, 256, and 512 Mbits, while 1-Gbit versions are expected by year's end and 2-Gbit devices are expected next year. A big driver has been digital cameras, compact/special flash-memory cards, and MP3 players. While NAND tends to have a slow first Read (1 µs), it compensates with faster burst or page-mode Reads (60 to 80 ns) following the first access.
In contrast, NOR flash typically targets faster Read applications (90 ns Read). These include cell phones, automotive control, PC BIOS storage, set-top boxes, and portables. In such applications, bit densities are on the order of 16/32 Mbits but are rising due to the need for more intelligence in many applications. For instance, adding Internet capability and a browser to a cell phone can easily double its nonvolatile memory requirements to 64 Mbits and beyond.
Moreover, for many applications, the CPUs execute directly from flash. So, flash-memory bus widths are expanding out to 32 bits to accommodate the latest system-on-a-chip and controller RISC cores. One vendor, Micron, has even implemented an SDRAM interface for its flash memory for easy interfacing. For applications that run faster than the flash bus rate, designers typically buffer the flash with a faster access SRAM. In fact, many vendors (for example, Fujitsu, Micron, and Samsung) have packed SRAM and flash into multichip packages for easy deployment. A few companies have even co-integrated the two on a single chip.
But flash hasn't abandoned its em-bedded roots. Designers can also select from many lower-density flash, EEPROM, and low-cost bit-serial flash and EEPROM chips to meet their system needs for nonvolatile storage. Typical applications include functions such as a boot ROM, special code storage, switch replacement, or parameter storage. Densities are on the order of 1 to 8 Mbits, with some need for up to 64 Mbits for the parallel-access devices, and up to 128 kbits for the bit-serial memories.
Perhaps, though, the distinction between NAND and NOR—slow versus fast and large versus small—is changing as new technologies push the two architectures together. For instance, NOR densities are going up with MLC technology.
The big change in flash-memory technology is MLC—the ability to store more than one bit per memory cell. A couple of years ago, Intel introduced the first MLC flash memory with its NOR StrataFlash technology.
Intel's StrataFlash stores 2 bits/flash cell by storing a graduated charge that can be sensed by a comparator that can distinguish between four voltage levels. These levels are assigned binary levels—00, 01, 10, 11—setting two cell-bit values (Fig. 1). MLC requires much better sense amplifiers and more of them, but that increase in area is compensated for by doubling the bit storage. Currently, Strata-Flash densities are 32, 64, and 128 Mbits. Engineering prototypes of devices with up to 512 Mbits have been described at various conferences. Reads are 110 to 150 ns for the first Read, and 25 ns for following page-mode Reads.
MLC techniques need precise charge placement. Moreover, that charge must be maintained in the dielectric for a long period of time, say 10 years. This requires careful voltage control and sensing.
Other memory vendors are climbing on the MLC bandwagon. STMicroelectronics has its own MLC flash, and SanDisk also employs its own MLC technology in the chips it uses in the memory cards it sells. Plus, most vendors have MLC on their flash-memory roadmaps, with products due out in the next year or so. These vendors include Hynix, Samsung, Sharp, and Toshiba.
AMD and its partner Fujitsu, with their joint company FASL, have developed an alternative multibit per cell approach for NAND flash. Instead of storing one of the n charge levels per cell, Mirror Bit stores two distinct bit charges. It does this by providing two different access paths to the Read or Write cell-bit storage dielectric. This method lets the cell address two different bit storage points (Fig. 2). But Mirror Bit obviously isn't expandable to 4 bits unless it uses MLC techniques as well.
AMD plans to release Mirror Bit flash products, starting with a 64-Mbit chip in the first quarter of next year, followed by a 256-Mbit part in the third quarter. Chip densities are expected to hit 1 Gbit. These will feature a Write buffer for faster programming and a page Read buffer for page-mode access times approaching 20 ns. Data retention is 20 years, with 1 million Write cycles/sector.
Another multibit cell technology is Nitrided ROM, or NROM. It can store 2 bits/cell and replaces the floating gates dielectric storage medium with a nitride trapping material sandwiched between two silicon-dioxide layers (ONO). The cells are supposedly much smaller than flash and require fewer mask steps during the manufacturing process.
The NROM cell bits can be individually erased and provide a Read speed of 80 to 90 ns. NROM has the advantages of low power dissipation and low programming voltages. Saifun developed the technology and is partnering with Infineon to build a 512-Mbit flash part. Hynix also works with Saifun's NROM.
Flash memory is deeply established as a common design technology and product base. Yes, flash memory has an ugly side. But it has been successful in spite of its requirement for complex, high-voltage, and long erase/program cycles. Why? Because flash provides low-power nonvolatile storage at a low cost—currently 40 to 50 cents/Mbyte, and that price will continue to fall.
Interestingly, the "ugly" but "cheap" memory technologies have won, even though they require other things to work. For example, SRAM is a relatively elegant, symmetric memory. But it was bypassed by both DRAM and flash, which require complex operations (DRAM with its refresh and flash with its block-erase and program requirements). Yet each deploys small memory cells, delivering the winning cost advantage.
However, emerging memory technologies promise to provide nonvolatility without the programming overhead that burdens flash. They may also provide an alternative to SRAM and DRAM. Some, like FRAM, have been around for many years. Advances in silicon and materials technology may now make them viable alternatives to flash.
It takes a lot for a new technology to overtake and replace an existing technology. For one, the existing technology continues to move up the silicon curve, so the challenger's advantages might shrink. For another, it takes time for a new technology to move into manufacturing and production, time during which the existing technology can up performance and lower cost.
Look at the x86 processor. A number of innovative RISCs and very long instruction words (VLIWs) challenged it. But by the time they hit production, the x86 had moved up the silicon curve, negating much of their architectural advantage. Case in point: the PowerPC. Another newer example, Intel's Itanium (IA-64), came out this year at over 800 MHz, while the recently introduced Pentium 4 has been demonstrated running at 2 GHz.
For the new, emerging nonvolatile memory, there are no guarantees of immediate success. Mainstream memory vendors are actively working on FRAM, MRAM, OUM, and PFRAM. Many are on the fast track to production. Even so, the time frame to hit the market as a viable, mainstream technology is between three and five years out.
FRAM, which has been around for quite a while, relies on a ferroelectric material (a Perovskite crystal or layered form), or a material that has a bi-stable center atom. Data is stored by applying a voltage that polarizes the internal dipoles to an "up" or "down." Those positions are ends of a hysteresis loop and can be read to find the stored value (Fig. 3).
Because the material is polarized and can hold that state, FRAM is nonvolatile. It provides a relatively fast random access Read and a fast Write with relatively low power consumption. But Reads are destructive. FRAMs must rewrite all cell contents after a Read access. Like flash, FRAM has limited memory rewrite cycles.
Today, Ramtron and Symetrix produce FRAM memory chips. Ramtron delivers 256-kbit chips, which are 3.3- and 5.0-V devices. The current design builds on a two-transistor, two-capacitor (2T2C) cell, but there's work involved in shifting to a more cost-effective 1T1C cell. Ramtron has teamed up with Fujitsu to develop a 1-Mbit FRAM with a 1T1C core cell. Infineon and Toshiba have additionally teamed up on FRAM development and are working on a 4-Mbit chip. Other companies working on FRAMs include Hitachi, Matsushita, Micron, NEC, and Samsung.
Magnetoresistive memory (MRAM) substitutes a magnetic material for the DRAM storage capacitor and flash dielectric to hold a programmed value. Because the material can hold its state, MRAM is a nonvolatile memory. Unlike FRAM, its Reads aren't destructive. Therefore, it doesn't require a restorative Write after a Read. Moreover, its Writes and Reads are symmetric with a 50-ns Read and Write. It also has no endurance limitations. Memory retention is on the order of a satisfactory 10 years. MRAM implementations can be done with supply voltages in the 2.5- to 3.3-V range. They can be run at a lower 1.8 V, however, which makes them attractive for low-power, nonvolatile consumer applications.
MRAM has a way to go before be-coming a mainstream technology. One problem may be material compatibility in integrating the magnetic material into a silicon process for reliable production. Additionally, MRAM requires a high Write current of up to 10 mA. That may be a problem for low-power operation, limiting Write widths to minimize the overall Write current. It means that programming MRAM may be a long-time affair. Plus, it takes a fairly large cell to build MRAM. For instance, Motorola's MRAM uses a metal junction transistor for each bit, but it also uses a transistor switch on each bit line and word line.
A number of vendors are working on MRAM. Motorola announced a 256-kbit CMOS chip fabricated using 0.6-µm design rules at this year's International Solid State Circuits Conference. The MRAM offered 35-ns Read and Write times (Fig. 4). The company expects to have 32-Mbit or larger MRAMs in production by 2004. Also, IBM has partnered with Infineon in an MRAM development effort.
Arthur Koestler defined creativity as bi-association, the bringing together of two separate things to create a new integrated whole. OUM does that. It combines silicon memory technology with the storage medium used for re-writable CDs and DVDs—chalcogenide material alloys (Fig. 5).
Chalcogenide, a metal alloy (Ge-SbTe), is used as the storage medium. The metal can take on crystalline conductive or amporhous nonconductive phases, which are conductive or resistive, respectively. State can then be stored by turning the bit material into a conductor or a resistor, a state that is detectable by measuring the bit cell's resistance. The bit state is changed by heating a small amount of the chalcogenide material using an electric current. When the material melts, it loses all crystalline structure and becomes a resistor.
This is a nonvolatile memory. Reads are nondestructive. The cell technology can run at low voltage, and it doesn't dissipate much power. It also supports 1012 Write/erase cycles. Write speed is on the order of 100 ns, which is good enough for many nonvolatile code-storage applications.
Ovonyx, working with Intel, has fabricated a 1-Mbit OUM test chip, built using 0.18-µm lithography. Intel has projected that the technology will easily scale down to 0.10 µm and lower and is working to achieve this. Other vendors working with OUM include STMicroelectronics and British Aerospace. The aerospace industry has demonstrated an interest in OUM for high-reliability, nonvolatile memory applications with a number of research projects exploring the memory technology.
Polymer memory builds on a polymeric ferroelectric material. This consists of a polymer material made up of polymer chains with a dipole moment. The dipole is used to store data by changing the polarization of the polymer. The polymer material is sandwiched between two metal lines, which expose the material to a measured voltage. This arrangement eliminates the 1T storage cell, as there are no transistors per cell. Moreover, these polymer layers can be stacked with a polymer layer between different bit layers (Fig. 6).
The individual polymer addressed bits are activated by word and bit lines. A common set of sense amplifiers in the CMOS base wafer sense the memory bit values. Reads and Writes are on the order of 50 µs.
Polymer memory can provide a very low cost per bit with a high chip capacity. The process is simple and can be easily integrated with standard CMOS processes. It uses a small cell size (4 λ2) and can stack up to eight layers for a high chip bit density. The cells don't require any standby power or any refresh cycles, but polymer memory isn't a fast access memory. Cell Read and Write times are on the order of 50 µs, which is adequate for disk-storage applications.
The polymer thin-film memory technology was developed by Thin Film Electronics. The company is owned by Opticom AS, with Intel holding a 6% interest. Thin Film Electronics offers nonexclusive licenses of its technology. Intel is helping to develop the technology, with an option to license the resultant technology. Intel's research is aimed at developing nonvolatile memory products.
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