Going With The Flow Speeds 3D Chips To Market

Going With The Flow Speeds 3D Chips To Market

Imec and Atrenta have teamed up to develop an advanced planning and partitioning design flow for 3D stacked ICs, facilitating accurate partitioning and prototyping early in the IC design process. These early moves are critical not only to achieve cost-effective 3D systems but also to get them to market quickly by cutting the number of design iterations. And 3D chips are attractive for a number of reasons.

The smaller that conventional chips get, the faster they are. But downsizing leads to the overwhelming operational challenge of heat buildup, which can reach levels where processing speed advantages are lost. Contributing to this thermal problem, high-density circuitry requires thinner wires, and resistance increases as a result of the size reduction of wire connects. This is where 3D chips will score.

There are two key design advantages. First, footprints are reduced. Second, the average wire lengths are shorter, so overall processor performance increases. There are distinct power advantages as well. 3D design is expected to significantly cut power consumption, and shorter wires create less parasitic interference. Reducing the overall power budget alleviates heat dissipation difficulties and generally reduces operational cost.

Bandwidth improvement is another important design aspect that is a prime consideration for today’s communications applications. 3D integration creates an opportunity to create more vertical vias between the chip layers, which allows the construction of wider-bandwidth buses.

Obstacles Ahead

That’s the good news about 3D chip design, but there are some technical hurdles to negotiate. The additional and complex manufacturing process involved to produce 3D chips inevitably raises the possibility of product defects occurring, so stringent product quality control must be implemented.

To be able to fully realise the application advantages of 3D chips, design methods and tools will have to keep pace. And that brings us back to this latest development from Imec and Atrenta.

Early planning and partitioning are essential in designing innovative applications with 3D stacked dies. The number of potential solutions for any given system design problem—front to front, front to back, silicon interposer, technology choice for slices, via configurations, partitioning, and so on—is diverse.

Identifying engineering solutions through multiple full designs is very expensive and time-consuming. It is therefore advantageous to perform accurate partitioning and prototyping early in the design process before detailed implementation begins.

When combining the design floor plans produced by Atrenta’s SpyGlass Physical 3D prototyping tool with the stress models developed by Imec, different scenarios can be assessed quickly and the best option can be chosen in advance of a full design implementation.



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