Interview: Cadence's Anirudh Devgan Talks About Parallel Timing Closure Signoff

Interview: Cadence's Anirudh Devgan Talks About Parallel Timing Closure Signoff

System-on-Chip (SoC) developers are creating larger and more complex solutions. Static timing analysis and closure is key to successful solution so timing sign off tools can have a significant impact on delivery of these solutions.

These types of tools are just one of many that Cadence provides to developers. I talked with Anirudh Devgan, Corporate Vice President, Silicon Signoff and Verification, Silicon Realization Group, about Cadence's new Tempus Timing Signoff Solution.

Wong: What are some of the challenges that Cadence's static timing and analysis tools encounter these days?

Devgan: There are three main challenges with signoff right now:

  • Performance and capacity
    • In recent years, design complexity has grown exponentially due to the increase in the number of modes and scenarios, bigger design sizes, higher performance and lower power requirements. Performance and capacity need significant improvements in order to meet these growing needs.
  • Accuracy
    • In order to increase accuracy in the end product, static timing has to correlate well with silicon.
    • We also need to reduce pessimism in order to make timing closure easier. Addressing pessimism can have a dramatic effect on time to closure, power and leakage consumed by the chip.
  • Design closure
    • Currently, design closure is very time consuming due to numerous iterations that are required between timing analysis and implementation to fix timing violations.

Wong: Have timing closure solutions kept pace with SoC complexity?

Devgan: There has been a lag in the past in terms of keeping pace with SoC complexity but the Tempus Timing Signoff Solution represents a significant advancement in timing signoff tool innovation and performance, leveraging multi-processing and ECO features to achieve signoff faster than with traditional flows.

Wong: Can you tell us about the Tempus Timing Signoff Solution?

Devgan: Cadence is announcing a new static timing analysis and closure tool called the Tempus Timing Signoff Solution. Our tool performs up to 10X faster than what is currently available in the market right now (Fig. 1). Tempus can also scale to handle full flat analysis of designs in the hundreds of millions of instances. It has an integrated signoff closure environment, which leverages innovative physically-aware ECO technology, which can help accelerate design closure by weeks.

Figure 1. The design closure process can utilize graph- or path-based optimization.

Wong: Why is this announcement important?

Devgan: This announcement is groundbreaking because we are solving a huge problem in the design implementation space. Timing closure and signoff is a massive challenge – as much as 40% of design implementation flow is spent in timing closure and signoff.

Wong: How does Cadence's solution scale?

Devgan: The Tempus Timing Signoff Solution is the first massively distributed parallel timing engine on the market,which can scale to utilize up to hundreds of CPUs. The number of CPUs refers to the number of CPUs on the computer server or set of machines on which you will run the Tempus software. Many companies have large server farms to run compute-intensive software jobs.

Because Tempus is both multi-threaded and massively parallel, it can run on multiple multi-core compute resources. While there is no theoretical upper limit on the number of CPUs, Cadence has run Tempus across as many as 64 CPUs.  At 32 CPUs, Tempus has analyzed tens of millions of cells in a single hour. Parallel computation also lowers the memory overhead. The observed memory footprint of Tempus allows design sizes in the hundreds of millions of cells with today's high end compute server configurations.

Wong: How does Tempus address the challenges in the market, making it a groundbreaking product?

Devgan: Tempus delivers unprecedented speed and performance by being able to run analysis in a massively parallel execution up to hundreds of CPUs, while maintaining full timing accuracy. Tempus can also handle extremely high capacity for full flat analysis in the order of hundreds of millions of instances.

Our tool has an extremely accurate delay calculation engine built for advanced nodes. It also has a path-based analysis engine that can reduce pessimism by 2-3 percent, which can reduce timing closure by weeks or help to lower power and area.

Tempus has an integrated closure environment that helps fix timing violations within the signoff environment with its physically aware ECO capability that can handle a hundreds of views concurrently.

Wong: Could you tell us more about Cadence's path-based analysis?

Devgan: Tempus has a new path-based analysis engine that leverages multi-core processing to reduce pessimism. It utilizes multiple CPUs, which speeds up the process and with its performance advantage, the Tempus Timing Signoff Solution enables broader use of path-based analysis than other solutions.

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