Smaller die sizes, low power consumption and a high level of integration are all promised by the MystiPHY110, a DSP-based, off-the-shelf core for a 10/100-Mbps Ethernet PHY. The core provides semiconductor and system vendors with a PHY building block to accelerate their end products’ time to market. It’ll see usage in existing applications, such as NICs, routers, switches and repeaters, and in emerging applications such as cable modems and set-top boxes and xDSL access boxes.The core, which has been fully implemented and verified in silicon, is easily ported to any standard CMOS process technology with 3.3V available for the I/O. In a 0.25-µm process, it occupies a 3.9 mm2 die area and has worst-case power consumption of 320 mW. It’s also scalable in two dimensions: the design easily migrates into smaller process technologies for increased port density and reduced cost per port, and is also scalable to Gigabit Ethernet on copper cable for applications requiring increased bandwidth. Pricing is based on a license fee and a per-port royalty.
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