Richard Kasica
Process Engineer Richard Kasica of NIST’s Center for Nanoscale Science and Technology holds a wafer of the type typically produced in the plasma-enhanced chemical vapor deposition chamber.

Error in Measuring Low Flows Could Cost Chipmakers Millions

Industry-standard calibration for flow meters is off and causing yields to drop for chip fabrication.

A new study by researchers at the National Institute of Standards and Technology (NIST) has uncovered a problem with an industry-standard calibration method that could lead microchip manufacturers to lose a million dollars or more in a single fabrication run. The problem is expected to get worse as chipmakers pack ever more features into ever-smaller spaces.

The error happens when measuring small flows of exotic gas mixtures. Minute gas flows are used in chemical vapor deposition (CVD), a process that takes place inside a vacuum chamber when ultra-rarefied gases flow across a silicon wafer to deposit a solid film. CVD is widely used to fabricate many kinds of high-performance microchips containing up to several billion transistors. CVD builds up complex 3D structures by depositing successive layers of atoms or molecules; some layers are only a few atoms thick. A complementary process, plasma etching, also relies on small flows of gases to create tiny features on the surface of semiconducting materials by removing small amounts of silicon.

The exact amount of gas injected into the chamber is critically important to these processes and is regulated by a device called a mass flow controller (MFC). MFCs must be highly accurate to ensure the deposited layers have the required dimensions. The potential problems are expensive in that chips with inaccurate layer depths must be discarded. 

“Flow inaccuracies cause nonuniformities in critical features in wafers, directly causing yield reduction,” says Mohamed Saleem, chief technology officer at Brooks Instrument, a U.S. company that manufactures MFCs. “Factoring in the cost of running cleanrooms, the loss on a batch of wafers scrapped due to flow irregularities can run around $500,000 to $1,000,000. Add to that cost the process tool downtime required for troubleshooting, and it becomes prohibitively expensive.” 

Modern nanofabrication facilities cost several billion dollars each, and it is generally not cost-effective for a company to constantly fine--tune CVD and plasma etching. Instead, the facilities rely on accurate gas flows controlled by MFCs. Typically, MFCs are calibrated using the “rate of rise” (RoR) method, which makes a series of pressure and temperature measurements over time as gas fills a collection tank through the MFC.

“Concerns surrounding the accuracy of that technique came to our attention recently when a major manufacturer of chip-fabrication equipment found they were getting inconsistent results for flow rate from their instruments when they were calibrated on different RoR systems,” notes John Wright of NIST’s Fluid Metrology Group, the group that conducted the error analysis.

Wright was particularly interested because for many years he had seen that RoR readings didn’t agree with results obtained with NIST’s “gold standard” pressure/volume/temperature/time system. He and his colleagues developed a mathematical model of the RoR process and conducted detailed experiments. The conclusion: conventional RoR flow measurements can have significant errors because of erroneous temperature values. The gas is heated by flow work as it is compressed in the collection tank, but that is not easily accounted for because it is difficult to measure the temperature of nearly stationary gas.

The NIST Team found that without corrections for these temperature errors, RoR readings can be off by as much as 1%, and perhaps considerably more. That might not seem like a lot, but low uncertainty is critical to attaining uniformity and quality in chip manufacturing. And the challenge is growing: Current low-end flow rates in the semiconductor industry are in the range of one standard cubic centimeter (1 sccm)—about the volume of a sugar cube—per minute, but they will soon shrink by a factor of 10 to 0.1 sccm.

Precise flow measurement is a particularly serious concern for manufacturing processes that etch deposited layers to form trench-like features. In that case, the MFC is often open for no more than a few seconds.

“Tiny variations in flow rates have profound effects on etch rates and critical dimensions of structures in very large-scale integrated circuits,” says Iqbal Shareef of Lam Research, a California company that provides precision fabrication equipment to microchip manufacturers. “So, we are extremely concerned about flow rates being accurate and consistent from chamber to chamber and wafer to wafer, and our industry is already headed toward very small flow rates.”

“We are talking about wafer uniformity today on the nanometer and even subnanometer scale,” Shareef said.

That’s very small. But it’s what the complexity of three-dimensional chip manufacturing increasingly demands. “Not so long ago, a 3D IC had four layers of metals,” says William White, director of advanced technology at HORIBA Instruments Inc., a firm that provides analytical and measurement equipment. “Now companies regularly create 32 layers and sometimes to 64. Just this year I heard about 128.” And some of those chips have as many as 3,000 process steps.

“Each 300 mm wafer can cost up to $400 and contain 281 dies for a die size of 250 to 300 mm2,” Saleem says. “Each die in today’s high-end ICs consists of about three to four billion transistors. Each wafer goes through one or two months of processing that includes several runs of separate individual processes, including chemical vapor deposition, etch, lithography and ion implantation. All those processes use expensive chemicals and gases.”

Many companies are already re-examining their practices in light of the NIST publication, which provides needed theoretical explanations for the source of RoR flow measurement errors. The theory guides designers of RoR collection tanks and demonstrates easy-to-apply correction methods. RoR theory shows that different temperature errors will occur for the different gases used in CVD processes. The NIST publication also provides a model uncertainty analysis that others can use to know what level of agreement to expect between MFCs calibrated on different RoR systems. For a copy of the NIST study, Errors in Rate of Rise Gas Flow Measurements from Flow Work, click here.

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