Electronic Design
Does Double Patterning Mean The End Of The World?

Does Double Patterning Mean The End Of The World?

Scanner resolution improvements have diminished since the 193-nm wavelength became commonplace. Today’s technologies are sufficient for 28-nm IC designs using immersion, but not beyond without additional assistance from the software solutions. Extreme ultraviolet (EUV) has been the next great hope for years, but it continues to be the next production solution for at least two nodes out—14 nm,  but far more likely at 10 nm.

The major foundry ecosystems are now using double patterning (DP) or multi-patterning to manufacture 20-nm IC designs. You hear lots of noise about how DP will completely change everything, make the designer’s life impossible, and so on. But is it really the end of the world?

Double Patterning 101

Below 28 nm, k1 is now falling below 0.25. (In Rayleigh’s equation, k1 below 0.61 expresses a high difficulty of achieving the desired resolution.) The existing optical process correction (OPC) software solution cannot, by itself, image the geometries.

However, a new technique of splitting the layout into two (or more) separate masks allows us to relax the layout pitch back to a k1 value that can be imaged with existing lithography/OPC solutions. This enables the creation of geometries and chips at 20 nm and below.

Unlike the introduction of OPC, however, which did not involve the designer, DP solutions impose new layout, physical verification, and debug requirements on the design and verification processes. The most basic impacts come from the constraints that DP puts on the physical layout of shapes in the design.

A fundamental concept called separation distance drives DP constraints. Basically, separation distance is a minimum space (separation) between any two polygons that will be placed on opposite masks. If adjacent polygons are on opposite masks, they can be much closer to each other than if they are on the same mask.

Separation distance usually isn’t a single spacing dimension, though, but several different measures of minimum separation. For instance, there may be separate minimum dimensions for one line tip to another line tip (tip2tip), or a minimum dimension between a line tip and a line side (tip2side), or another minimum dimension between one line side and another (side2side), and so on. It is also important for designers to understand that separation distance is completely different from the minimum allowed space between polygons required by design rule checking (DRC).

Pitch splitting, the form of DP being used at 20 nm, uses litho-etch-litho-etch (LELE) techniques, including a variation in which the original drawn polygons can be cut into pieces and stitched (overlapped at their cut locations) to enable additional decomposition options. Figure 1 illustrates how each technique is used to decompose (split) the original drawn layout into separate layers, either automatically by EDA software or manually by the designer.


Fig 1. Designers can take advantage of the different types of double patterning layout decomposition. The different colors indicate the design elements assigned to each mask.

Moving To 20 nm And DP?

As in all prior technology node transitions, the cost of masks and wafers will increase at 20 nm. The reason is simple—the cost of research & development (R&D), EDA, and physical manufacturing is higher, and suppliers need to see a reasonable return on their R&D investment to enable the production of smaller and/or higher-performing chips. While the cost for DP is not the sole source of this increase, it is one part of the additional costs incurred as companies move to new nodes.

Fablite and fabless companies benefit by more die per wafer or increased functionality/performance for their new products. Consistent with the last 30 years, moving to a new node means increased costs (Fig. 2). But in exchange, significantly more value is delivered to the consumer, so everybody wins.


Fig 2. Wafer prices have increased substantially with the jump to the 20-nm node and could go even higher with the expected move to 14 nm and then 10 nm. (courtesy of IBS)

There is a lot of fear in the industry that designing for DP will be a nightmare, but will it really be that bad? Major foundry ecosystems such as TSMC and ISDA are actively working to make it as easy as possible to do business with them and to minimize the impact of DP on their customers’ designers.

The foundries and the major IP suppliers are all creating 20-nm intellectual property (IP) libraries that are already DP-compliant. Will there be additional work for the designer? Yes, just as there is for every technology node.

Industry-wide, there are usually 25% to 35% more DRC checks at each new technology node. Checking to ensure a design can be decomposed will be part of all foundry signoff DRC decks and will be mandatory for tape-out to your foundry.

But how much additional work will it be, really? The industry-average 20-nm DRC deck is expected to have about 3800 checks (Fig. 3). Out of this, only 0.8% (or about 30 checks) will be for DP. This is paltry compared to the approximately 600 additional non-DP DRC checks that will be added as part of the normal increase seen in DRC complexity node over node.  


Fig 3. The number of DRC rules will top 5000 and the number of operations will surpass 30,000 at the 16-nm and 14-nm nodes.

The result markers for DP errors will look slightly different than those for standard DRC results, but this difference is primarily to provide more hint information to the designer for more efficient error debugging. Still, since DP will just be more checks in the signoff DRC deck, for designers, a DP error will be just one more thing to fix.

Preparing For 20 nm And DP

Some EDA suppliers are talking about how DP changes everything and how only their tool can properly check DP. What they fail to mention is that DP will simply be part of signoff DRC, and a diminishingly small part at that.

I’m not saying that DP isn’t important or that the EDA industry and other ecosystem suppliers shouldn’t see a return on the huge investment they have had to make to create the new DP processing and verification engines and process/capital equipment technology that enables the jump to the next technology node. What I am saying is that because DP is an integral part of DRC, the choice you make for a DP solution should be made using the same criteria you have always used to pick your DRC supplier:

  • What tool does the engineering team within your foundry use for DRC verification? Using the same tool means you will always get the same results as your foundry, with no last minute surprises.
  • What decks are always available first from your foundry and have the most maturity?
  • What DP tool will run simultaneously with your DRC tool? You don’t want to debug DRC errors with one tool and then have to debug DP errors on a second one, iterating back and forth to achieve both a DRC-clean and DP-compliant design.
  • Does your DP tool handle these checks like it does other complex DRC checks in a manner that allows you to check and correct your errors simply and completely?


Moving to 20 nm will introduce new DP checks that are integral to the mandatory signoff DRC deck you already rely on to ensure your design will manufacture well. Designers will run the same signoff DRC deck from the supplier they have always trusted. That deck will simply have new checks that ensure DP decomposability.

The creation of a DP ecosystem, enabling the move to 20 nm and below, has required significant investment by suppliers. But the actual impact on designers is expected to be modest. Since DP is an integral part of signoff DRC, designers will stay with the solutions they (and their foundries) currently use for signoff. Yes, DP will be a bit more work, but it will not be the end of the world. Whew!

TAGS: Digital ICs
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