FPGAs are now system components. They can serve as a logic subsystem or as a processor platform. Not only have densities risen to the 6- to 10-Mgate range, but functionality has also shifted from pure logic to a full spectrum of implementation functions. Xilinx's Vertix II delivers platform-level capabilities. This second-generation Vertix FPGA supports logic densities to a claimed 10 Mgates, but it also delivers in-system implementation functions and capabilities. These span from 200-MHz multipliers and tailored embedded IP to system-wide routing and clock-management functions.
Vertix II was designed to serve as a system element. It supports a range of I/O connections, up to 19 single-ended and six differential standards, with a programmable sink current of 2 to 24 mA per I/O. The single-ended I/O is supported with the XCITE digitally controlled impedance using programmable on-chip termination resistors. There is no off-chip termination. Off-chip memory interfaces include 400 Mbits of DDR SDRAM, 400 Mbits of FCRAM, 333 Mbits of QDR SRAM, and 600 Mbits of Sigma RAM.
This FPGA is tuned for large-scale subsystem implementations. It builds on an extended interconnect technology with a segmented routing structure. Also, the Vertix II employs a hierarchical routing scheme. Each logic block (CLB, IOB, DCM) interfaces to a switch matrix that links to the routing resources. The resources deliver predictable routing delays, independent of logic fanout. Xilinx's Active Interconnect Technology consists of global, hex, double, direct, and fast routing levels.
A new high-performance clock routing scheme with up to 12 Digital Clock Manager modules supports routing. The modules provide a zero-delay clock buffer, a precision clock edge to 1%, programmable clock frequencies, and special EMI control.
To build complex subsystems, the FPGAs support hard-IP insertion with special adaptable-routing features. The FPGAs also have built-in hard IP, such as 18- by 18-bit multipliers, supporting carry-look-ahead logic, and SRAM blocks that come in 18-kbit, dual-port, synchronous chunks. The SRAM blocks can be configured as single or dual port with different data/address aspect ratios.
Vertix II builds on the classic Xilinx CLB base. Each CLB element consists of four logic slices and a switch matrix, with each slice deploying two four-input function generators, wide-input multiplexers, and a local register. Each function generator serves a four-input logic function, or as 16 bits of SRAM, or as a 16-bit shift register. The Vertix II CLB includes multiplexer logic that can take in up to eight inputs. Additionally, the multiplexers can implement a 4:1 (one slice), 8:1 (two slices), 16:1 (four slices), or a 32:1 (eight slices) multiplexer function.
The first members of the Vertix II family are sampling now. These include the 40-kgate XC2V40, the 1-Mgate XC2V1000, and the 6-Mgate XC2V6000. They cost less than $10, $70, and $1200 respectively in 100,000-unit lots.
Xilinx Inc., 2100 Logic Dr., San Jose, CA 95124-3400; (408) 559-7778; www.xilinx.com.