The growth in high-performance computing and AI in advanced chip architectures is creating issues when it comes to intra-chip data management, especially as they migrate to chiplet-based topologies. Addressing this chip-level issue, Avicena announced its scalable LightBundle chiplet interconnect solution. It offers ultra-high-density die-to-die connections with a multi-Tb/s/mm shoreline bandwidth density at sub-pJ/bit energy efficiency.
In this podcast we talk to Bardia Pezeshki, founder and CEO of Avicena, about the issues of intra-chip data management and his company’s solution.
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An Army veteran, Alix Paultre was a signals intelligence soldier on the East/West German border in the early ‘80s, and eventually wound up helping launch and run a publication on consumer electronics for the US military stationed in Europe. Alix first began in this industry in 1998 at Electronic Products magazine, and since then has worked for a variety of publications in the embedded electronic engineering space. Alix currently lives in Wiesbaden, Germany.
Also check out his YouTube watch-collecting channel, Talking Timepieces.
