Electronic Design

IC Implementation Platform Promises Two-Day Full-Chip Turns

Much has changed in IC implementation, even in the six short years since the launch of Magma Design Automation. When Magma began, the current state-of-the-art IC designs led its technologists to pursue a path dominated by timing closure at block level. The result was a strategy that led Magma to drive physical synthesis into the design flow to an extent that hadn’t before been seen.

But in the ensuing rush to embrace 90-nm (and now 65-nm) process technology, ICs became much larger. Full-chip design closure has become a laborious process of divide and conquer. EDA tools provided the productivity required for the block level, but still lag for full-chip closure. With design costs for a typical 65-nm design ranging from $20 million to $30 million, it’s getting very difficult for anyone to justify the price tag, and more difficult still to actually realize a profit.

With the release of its Talus IC implementation suite, Magma seeks to address the cost explosion in IC design while simultaneously delivering more automation to the design process. “Our goal was to deliver the capability to create a large design in two days. Achieving a two-day turnaround, whether or not the tool uses hierarchical methods or any other techniques, is our problem, not the designers’ problem,” says Rajeev Madhavan, Magma’s chairman and CEO. “To shorten the chip-design cycle and lower the attendant costs, designers need more automation and a more seamless flow that masks much of the complexity.”

To embody these goals, Talus provides a complete RTL-to-GDSII flow that concurrently analyzes and optimizes timing, area, power, signal integrity, and yield (Fig. 1). It performs full-chip RTL synthesis, automated power-grid design and synthesis, full-chip clock synthesis, and automated distributed processing.

In the Talus flow, floorplanning is performed in an automated physical-synthesis process. Using a new constraint set that Magma calls relative placement constraints, Talus eliminates the traditionally labor-intensive and time-consuming floorplanning and prototyping processes (Fig. 2).

Design for variability on complex designs is supported through concurrent multi-mode/multi-corner and native on-chip variation analysis with timing and crosstalk noise optimizations. The tool’s timing-analysis capabilities eliminate the need for iterative analysis and optimization runs to meet multiple mode and corner constraints. Talus also incorporates sophisticated routing algorithms developed by Magma in collaboration with IBM and the University of Bonn, Germany. The entire flow is lithography-aware, which minimizes the key source of deterministic variability in 65- and 45-nm flows.

Talus’s Automated Chip Creation methodology enables design creation with as little as 10% of the design’s final RTL. While earlier methodologies performed clock synthesis at block level and tied it together at the full-chip level, Talus first identifies the top-level timing constraints that meet block-level timing budgets, which helps avoid timing violations during full-chip integration. For each subsequent RTL change, Talus creates multiple floorplans to enable designers to observe, in real time, the impact of those changes on chip size.

It’s been standard practice for some time to overdesign power grids, which can result in an undesirable hit on area. Talus accounts for power requirements in each region of the design and makes decisions on where the power mesh needs to be heavier and where it can be scaled down.

Two products comprise the Talus flow. Talus LX synthesizes the design RTL for given timing, power, and placement constraints and automatically generates physical partitions as well as power- and clock-grid prototypes. With Talus LX, designers can quickly explore the design space and implement an optimized design without detailed knowledge of physical design.

Talus PX performs complete physical implementation of the design including near-abutment layout, final physical partitions, power and signal routing, and chip-level clock-tree synthesis. Between the two products, manual effort is largely eliminated; beta testing with a customer design has delivered a 17% area reduction compared with manual design efforts while producing GDSII from the original RTL in just two days.

Production versions of the Talus tools are scheduled to ship in September. Magma has not yet set pricing.

Magma Design Automation Inc.
www.magma-da.com

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