Electronic Design

Signal-Integrity Analysis Tool Leads Way To SoC Timing Closure

At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding unexpected and undesirable electrical effects that wreak havoc with signal integrity. SignalStorm SoC, a signal-integrity analysis tool, aims to address these issues by accounting for propagation delay, voltage drop, and crosstalk effects through hierarchical delay calculations.

The tool enables SoC designers to determine the impact of signal-integrity effects on path delays with high accuracy. It's accurate to within 2% of Spice with runtimes that are four to 20 times faster than other signal-integrity tools, while consuming 80% less system memory.

In analyzing SoC designs, SignalStorm SoC integrates all delay factors, including interconnect delays, in-stance-specific IR drop effects, and crosstalk effects. It supports industry-standard .lib libraries and static timing analyzers such as Synopsys' PrimeTime. In doing so, it offers time-quantized calculation of Ceff for higher accuracy as well as accurate handling of multidriven nets and meshes.

That latter form of analysis is facilitated by an optional advanced Effective Current Source Model (ECSM) capability for aggressive, complex design styles. These model types gather driver information during library characterization, which yields more accuracy than reverse engineering from delay and slew tables. Interconnect parasitics are derived using Simplex's extraction technology, while IR drop data is extracted using the company's VoltageStorm SoC technology.

SignalStorm SoC is available now in various package configurations and library options. Pricing starts at $50,000.

Simplex Solutions Inc., www.simplex.com; (408) 617-6100.

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