System-on-a-chip (SoC) design is a complex effort that encompasses many disciplines, from circuit design to thermal management to testing. When working with a design library from a particular ASIC supplier, creating an SoC solution can be relatively straightforward because the library’s circuit building blocks are designed to work together. However, the challenge gets more complex when designs must incorporate blocks of intellectual property (IP) acquired from third-party suppliers into the design flow. Such blocks may follow different design rules, have incompatible interfaces, and require unique test support. However, there are ways to mitigate the potential incompatibilities. Sticking to a set of guidelines will smooth the IP’s path into the design.
Today’s multi-megagate SoC designs often include many different blocks of IP to reduce design time. In the example shown in Figure 1, the left half of a highly integrated SoC combines a RISC processor with associated instruction and data caches, interrupt and DMA controllers, a double-data-rate SDRAM controller, a local scratchpad memory (8 kbytes), and JTAG test support. The other half of the chip includes complex I/O functions such as a 10/100/1000 Ethernet media access controller (MAC), a PCI interface block, a USB interface, and possibly a Bluetooth baseband controller. These blocks can either be selected from the SoC vendor’s design library or imported into the design from an independent IP supplier.