Electronic Design

Unified Verification Flow Takes Higher Ground

Cadence's new verification platform provides native support for high-level languages and transaction-level virtual prototypes.

Cadence's new verification platform provides native support for high-level languages and transaction-level virtual prototypes.

Verification of systems-on-a-chip (SoCs) is hard and getting harder. Not only are today's verification flows fragmented, but the flows are cumbersome. With more than 70% of silicon re-spins containing functional errors these days, verification clearly remains a bottleneck.

In rolling out its Incisive verification platform, Cadence brings together a unified methodology based on a single-kernel architecture that can compress overall verification cycles by as much as 50%. Almost as importantly, the platform provides native support for Verilog, VHDL, SystemC, the SystemC Verification Library, the Sugar property specification language, algorithm development, and analog/mixed-signal designs.

The Incisive methodology begins with an architecturally accurate, transaction-level Functional Virtual Prototype (FVP). A transaction-level FVP can run 100 times or more faster than RTL.

"The goal is to capture specifications, and design intent, at the transaction level," says Mitch Weaver, Cadence's VP of verification marketing.

FVPs provide a full-chip environment for block-level verification. The methodology supports both top-down and bottom-up approaches. When block-level verification is complete, FVPs serve as the vehicle for integrating verified blocks and running full-chip, implementation-level verification.

The latter is supported by what Cadence calls "Acceleration-on-Demand." Three flavors of the Incisive platform are offered, beginning with a software-only unified Incisive simulator (one-year licenses start at $27,000). The next level is Incisive-XLD, a package that provides the runtime option of using up to 10 seats of Incisive or as many as 1 million gates of acceleration capacity (pricing starts at $200,000). Acceleration is hosted on a local or remote Cadence Palladium accelerator/emulator.

The third offering is Incisive-XLD Base, which makes the Palladium accelerator available full-time (starts at $360,000). Cadence has lined up considerable third-party verification IP support for the platform.

Cadence Design Systems Inc.
www.cadence.com

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