Even after 25 years of electronic design automation (EDA), a very high percentage of the layout for ICs shipped today are still completed by hand!
Well, not by hand exactly, but with a good deal of manual effort using rudimentary layout editors. For high-volume consumer chips such as memory, LCD drivers, and imaging devices, cost — that is, area and yield — are the drivers for customization, while for microprocessor designs, it is performance. Many of these designs are implemented at the latest technology nodes and, like their standard-cell brethren, they are gaining in size and complexity. But curiously, there has been little improvement in the design tools available to designers of custom logic.
Today’s custom digital designs need better automation and I believe that now is the time for what I’ll term “custom design automation.”
In part, the lack of suitable automation for custom layout is due to the fact that it is extremely hard to devise automation to match the skills and requirements needed to tackle this domain. Another reason is simply that the EDA industry has been otherwise busy and focused on the needs of large digital standard cell-based designs (read: ASICs), leaving the custom layout designers to fend for themselves.
It is no surprise that the custom part of designs takes a greatly disproportionate percentage of the design time. For such parts, it is not unusual to find that up to 70% of the design time will be taken for effectively hand-drawn layout. It is on significantly improving the productivity of custom layout engineers that a small but growing group of companies such as Pulsic is focused.
In the past, such designs have been developed from the bottom up — leaf cells of transistors first, then layer upon layer of logic building to the top level. The thinking behind a modern custom design automation methodology is to reverse this approach and, instead, promote a top-down and hierarchical approach. It introduces floorplanning and hierarchical design methodologies as well as layout tools that allow engineers to plan the control logic. These tools are basic essentials that modern custom digital designs such as the latest flash memory require.
In the custom world, such control logic is never standard and contains a rich mix of standard cells, custom cells, and transistors. All three implementation techniques need to be handled simultaneously in the layout, and automating the layout of such custom designs requires specialist approaches to do so. This is true not only in placement but also in routing, where the standard techniques of the ASIC domain are no longer valid. Not only are these individual capabilities needed, but also significant productivity gains are achieved if all these capabilities are tightly integrated. By bringing the individual components of planning, placement, and shape routing into a single hierarchical environment, significant productivity boosts on the order of 50% or more can be realized.
Therefore, it’s high time for change. And, here is my prediction: It won’t be long before a custom design automation approach will be touted and then implemented throughout the electronics industry.