Test Vision 2020, scheduled for July 13-14 in San Francisco in conjunction with SEMICON West 2016, has issued a call for papers. Organizers report that the conference typically has more than 100 participants, assuring access to a wide range of expertise and experience. This year’s theme is “Adapting to the New Realities of Test.”
Organizers further report that while the semiconductor classic front-end Moore’s Law physical and cost scaling is near an end, the pace to adopting advanced packaging technologies such as 2.5D and 3D is accelerating. The focus is now shifting to feature integration density, whether through on-die 3D stacking or heterogeneous integration of different die in the same package. This trend is significantly impacting the wafer and final-test strategy and cost considerations.
Test is now evolving from primarily a pass/fail exercise to a process that is adapting to the needs of newer devices, organizers report, taking the form, for example, of repair and calibration to improve yield or optimize test and production flows based on big data gathered during the manufacturing process.
With these topics as the backdrop, organizers intend to spark lively debates. To this end, they are seeking papers that offer thought-provoking and even controversial ideas as Moore’s Law and More than Moore packaging advancements call for new innovations in DFT, test engineering, wafer probing technology, and device manufacturing.
Test Vision 2020 will address questions such as these:
- What can we do differently to provide probably-good-enough testing cost effectively?
- What R&D tools are needed for today’s and tomorrow’s devices?
- What will the test cell (ATE plus handlers or probers) need to look like in 2016 and 2030?
- Are today’s technologies adequate for the future?
- If not what can we do to close the gap?
Representative topics include, but are not limited to
- critical future-proof ATE capabilities,
- test methods for future defects,
- 5D/3D device testing ideas and techniques,
- power testing needs for green technology,
- application level test,
- high-speed I/O test,
- standards,
- impact of IC power management on test,
- calibration and repair techniques,
- MEMs device testing,
- ideas in manufacturing flow optimization,
- RF and SOC testing trends,
- adaptive and concurrent testing challenges,
- automated test program generation,
- impact of new fab processes on test/manufacturing,
- wafer-probing technologies,
- low-cost application focused testers,
- software for ATE, and
- security impacts on test (cyber security/test, etc.).
Authors are invited to submit draft presentations, extended abstracts (500 words), or full papers. Submissions must be received by April 4, 2016. Authors will be notified of the disposition of their presentation by May 2, 2016, and must submit the final presentation by June 23, 2016, for inclusion in the memory stick that will be provided to the attendees.
In addition, test experts and students are invited to submit posters.
Visit www.TestVision2020.com for more information.
