A Very Wide Loop Bandwidth Technique for High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series.

As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher performance than ever before, and they’re placing greater demands on the frequency sources for these systems. Such systems are moving higher in frequency (millimeter-wave, or mmWave, and possibly THz regions), tuning wider bandwidths (BWs), processing more complex waveforms using more elaborate modulation schemes, and operating in fast tuning modes.

This is happening in both the commercial and military arenas. Examples include satellite communications and repeaters, terrestrial wireless systems such as the present 5G^15,16 and eventually 6G^17,18 protocols, and tactical line-of-sight radios, among others. Therefore, the frequency sources, and particularly the local oscillators (LOs), for these systems must also move commensurately higher in frequency and deliver higher performance in terms of low phase noise (our priority interest), low spurious, and fast tuning speed.

In some cases, LOs using direct (mix-multiply-divide, MMD) synthesizers are needed to achieve this performance, but they’re usually not lowest in SWaP, cost and complexity. However, in many cases, LOs using indirect (phase-locked-loop, PLL) synthesizers can be used with excellent results. They rival the performance of direct synthesizers and are usually lowest in SWaP, cost, and complexity, which is the thesis here.

For the case of PLL synthesizers and, concerning a priority interest in low phase noise, this means that for the relevant PLLs, as their operating frequencies become higher, their loop BWs must become commensurately wider (i.e., fractional loop BW is the ultimate interest) to achieve low phase noise. Also, by applying the special technique shown here, it’s possible to achieve very wide loop BWs in such synthesizers, which can’t be achieved by conventional methods.

By “relevant PLLs,” we mean those PLLs comprising the synthesizer that significantly influence the operating band phase noise. For multiple PLL systems, this usually means the output PLL, which is normally the highest frequency PLL. For single PLL systems, the situation is obvious.

In addition to utilizing very wide loop BWs, the use of unity closed-loop (CL) gain along with only internal (within any relevant PLL) multiplication also assists in achieving low phase noise. The technique is applied here to an example synthesizer that’s a single-loop (thereby having only one relevant PLL, simplifying the situation), Type 2 - 2^nd Order system with a 1st Order active proportional-integral (PI) loop filter, which is used as an LO in an actual working and fielded high-performance receiver.

This topology is widely employed, so the technique has broad applicability. It can also be applied to PLLs using other topologies with appropriate modifications. However, we will restrict our discussion to the topology of our example mentioned above. Also, the example synthesizer is based on analog hardware because of the high-frequency loop dynamics involved, rather than digital (or computed) hardware/software approaches, which are limited by present-day computing speeds.

In Part 1 we described the technique and presented the example synthesizer incorporating the technique. In Part 2, we discuss the synthesizer general design approach and detailed design, which incorporates the technique.

General Design Approach and Block Diagram

Initially, complete system (receiver) and subsystem (1st LO) analyses were done, with priority interest in low phase noise, followed by a trade study to decide on the general design approach for the synthesizer, i.e., either direct (MMD) or indirect (PLL), along with the number of MMDs or PLLs (loops) needed, respectively. The indirect (PLL) approach was decided upon, for the following reasoning: 

• The direct approach typically has lower phase noise and faster switching speed (although spurious can be somewhat more troublesome) than with the indirect approach, but has higher SWaP, cost and complexity. This approach wasn’t chosen based mainly on the latter issue.
• The indirect approach typically has higher phase noise and slower switching speed (although spurious can be somewhat less troublesome) than with the direct approach, but has lower SWaP, cost and complexity. This approach was chosen based mainly on the latter issue.

Then, continuing with the analyses and reasoning above, along with the specifications described in the “Example Synthesizer Application and Specifications” in Part 1, it was decided on the following detailed implementation for our PLL approach:

• Topology:
  • Single loop (only one PLL deemed necessary)
  • Type 2 - 2^nd Order system with a 1^st Order active PI loop filter
  • Translational feedback (FB) - providing unity (N = 1 or 0 dB) CL gain
  • Internal (within PLL) multiplication
• Acquisition: Aided (necessitated by its wide tuning BW and unity CL gain), using window steering circuit
• Loop BW, f_G (= ω_G / 2π), chosen for lowest integrated SSB phase noise: f_G = 15 MHz
• Natural resonant freq, f_n (= ω_n / 2π), and damping factor, ζ (recall f_G = 15 MHz):
  • f_n  = 9.677 MHz (using rule-of-thumb f_n = f_G / 1.55 for ζ = 0.707²), ζ = 0.707
• 1^st Order active PI loop filter (detail): Dual-path topology, i.e., a 1^st Order dual-path active PI loop filter, since a single-path topology (normally an op amp) would not support the very wide loop BW
• Translational FB (detail): Dual conversion (two sequential converters)

So, in summarizing, it was concluded that the synthesizer would be of the PLL variety with the following topology: Single Loop, Type 2 - 2^nd Order system with a 1^st Order dual-path active PI loop filter, dual conversion translational FB, internal multiplication, aided acquisition, loop BW of 15 MHz, natural resonant frequency of 9.677 MHz, and damping factor of 0.707. For discussion purposes, the synthesizer will be broken up into two sections: the “PLL Section” and the “Reference - I/O - Power Section.

PLL Section

Figure 1 shows the block diagram of the PLL Section.

This section begins with the phase frequency detector (PFD), which has a 1,300-MHz BW, up and down (i.e., two) voltage outputs (each output being differential, for a total of four voltage outputs), a very low SSB phase-noise floor factor of −153 dBm/Hz, no dead zone, internal polarity control, and lock detection capability. It feeds a gain control circuit providing approximately 0 to −7.5 dB of adjustment in 16 steps of 0.5 dB, which then feeds the 1^st Order dual-path active PI loop filter.

The loop filter contains a low-noise op-amp integral (integrating) amplifier in parallel with a discrete, low-noise, differential proportional amplifier, along with an aided acquisition (window steering) circuit. The output of this system, after being summed and filtered, then controls a 5- to 10-GHz wideband VCO that feeds an effective X4 internal multiplier for the 22.5- to 39.9-GHz synthesizer output. Finally, we have the dual conversion translational FB system completing the loop.

These three design techniques provide unity CL gain and very low phase noise. Better phase noise might be possible using a switched, narrowband VCO stack. However, a single wideband VCO was used for lower SWaP, cost, and complexity, while providing phase noise that met subsystem (and hence, system) specifications with reasonable margin.

Reference - I/O - Power Section

Figure 2 shows a simplified block diagram of the Reference - I/O - Power Section.

This section begins with a state-of-the-art 100-MHz OCXO that goes through a 2X splitter. One output of the splitter drives an effective X4 multiplier to provide the 400-MHz PFD reference to the PLL section and the other output drives an effective X16 multiplier that goes through another 2X splitter.

Both outputs of that splitter drive two control blocks, Control Block 1 and Control Block 2, where each of these produces its respective control lines, Control Lines 1 and Control Lines 2. The lines drive their respective converter blocks, Converter Block 1 and Converter Block 2, in the PLL Section.

Finally, we have the Power & I/O (Control & Status) Interface, which is fairly typical, showing those functions that interact internal to the synthesizer and those that interact external to the synthesizer. Also labeled are those functions that interface with the local section (Reference - I/O - Power Section), PLL Section, and both sections.

The 1st Order dual-path active PI loop filter is the key component of the synthesizer that allows it to achieve its very wide 15-MHz loop BW (Fig. 3).

The op-amp integral amplifier is standard and not a contributor to the very wide loop BW. However, the differential proportional amplifier is unique, and it’s the sole contributor to the very wide loop BW (Fig. 3 and close-up in Fig. 4). This is because of its high frequency operation; for the example design, at a bias point of 3 V – 3 mA, the insertion gain of each device is 15 dB at 300 MHz with a transition frequency (f_T) of 2 GHz (as indicated by the S-parameter data from the device datasheet).

It also provides a great deal of flexibility, since its gain (and other parameters) can be adjusted. With the adjustable gain, wider loop BWs can be achieved (to perhaps 100 MHz or more, if ever practically needed) if not limited by the VCO tuning port modulation BW. As good design practice, each input to the amplifier is fed by a 50-Ω source impedance from each output of the PFD, which varies slightly with PFD gain control setting. The amplifier output is then terminated with a 50-Ω load impedance at the summing point with the op-amp integral amplifier.

PLL Section Detailed Design and Schematic Diagram

The design of any PLL and, hence, our single-loop PLL synthesizer, can basically be systemized into a straight-forward sequence of standard steps.² Except for the special loop filter, the detailed design of the loop is a fairly straightforward textbook example for a Type 2 - 2^nd Order system with a 1^st Order active PI loop filter. Some of these design steps were already determined in the “General Design Approach and Block Diagram” section above, and they’re repeated here for comprehensiveness and with further clarification. These design steps are:

1. Interpret and understand specifications:

• As discussed in the “Example Synthesizer Application and Specifications” section in Part 1.

2. Select general approach and implementation:

• As discussed in the “General Design Approach and Block Diagram” section above.

3. Select components (ones with major impact to performance - all are low-noise/low-power types): Reference oscillator (actually in Reference - I/O - Power Section), VCO (K_o = K_v/s), PFD (K_ϕ), FB divider (K_n = 1/N), Loop filter / Error amplifier (F(s) - comprised of individual proportional and integral error amplifiers):

• Reference oscillator: Major electronics manufacturer’s state-of-the-art 100-MHz OCXO.
• VCO: Major electronics manufacturer’s high-frequency octave BW (5-10 GHz) VCO, along with X4 internal (within PLL) multiplier, to produce effective:
  • K_v = 875 MHz/V => 5.498(10⁹) rad/S/V @ 39.9 GHz (upper band edge)
  • K_v = 1,355 MHz/V => 8.514(10⁹) rad/S/V @ 31.3 GHz (middle of band)
  • K_v = 1,635 MHz/V => 1.027(10¹⁰) rad/S/V @ 22.5 GHz (lower band edge)
• PFD: Major electronics manufacturer’s wideband (1,300 MHz) low-noise (−153 dBm/Hz SSB phase-noise floor factor) PFD, along with gain control, to compensate for Kv variations across the VCO band (keeping K_ϕK_v = constant) to produce effective:
  • K_ϕ = 5.556 mV/deg => 0.318 V/rad @ 39.9 GHz (upper band edge - gain at maximum)
  • K_ϕ = 3.582 mV/deg => 0.205 V/rad @ 31.3 GHz (middle of band - gain at mid-range)
  • K_ϕ = 2.970 mV/deg => 0.170 V/rad @ 22.5 GHz (lower band edge - gain at minimum)
• FB divider: None - dual conversion translational FB used, giving N = 1, K_n = 1/N = 1.
• Proportional error amplifier: Major electronics manufacturer’s bipolar differential pair (low-noise, low-power, high-frequency, compatible power-supply requirements, adequate output voltage/current drive capabilities).
• Integral error amplifier: Major electronics manufacturer’s high-performance op amp (low-noise, low-power, unconditional stability, compatible power-supply requirements, adequate output voltage/current drive capabilities).

4. Determine PLL topology:

• Since phase continuity for adjacent channel step phase and frequency is specified, a Type 2 PLL is required. A 2^nd Order (excluding any extra high-frequency poles used for additional filtering) PLL will be used because it’s (theoretically) unconditionally stable, is the minimum order that can be used, and is less complex than higher-order systems. Also, a 1^st Order dual-path active PI loop filter will be used since a standard active PI loop filter (normally a single op amp) will not support the very wide loop BW. These three factors make the PLL simple, easily analyzed, and unconditionally stable. In summary, then, the PLL will be a Type 2 - 2^nd Order system with a 1^st Order dual-path active PI loop filter. The special loop filter will be implemented by using a standard op amp for the integral part and a differential amplifier for the proportional part.
• As shown in Figures 3 and 4, the differential amplifier in this case isn’t a true differential amplifier, but rather a pseudo-differential amplifier. We use the prefix “pseudo-” because it doesn’t have the two emitters coupled together biased with a true current source. Rather, it has each emitter independently biased with a relatively high-value “long tail” resistor, approximating a true current source, and a low-value cross-coupling resistor between the two emitters, which partially controls the gain. This circuit is a standard substitute for a true differential amplifier because of its simplicity and it works well for this application.¹¹ The bias point for each device (both devices in a single package) was chosen from the datasheet at 3 V – 3 mA based on S-parameter data for these conditions. Then the gain of the amplifier using our implementation is given by G = (R₃/2R₂).

5. Determine standard parameters ω_n and ζ from the specifications:

• ω_n (actually f_n) and ζ are determined from phase noise, switching time, and stability specifications. For this case, phase noise is the priority. These were determined in the “General Design Approach and Block Diagram” section above to be (recall f_G = 15 MHz):

f_n = 9.677 MHz (using rule-of-thumb f_n = f_G / 1.55 for ζ = 0.707²) = 0.707

6. Equate the standard-form OL transfer function to the circuit-constant OL transfer function, which gives standard parameters f_n and ζ as functions of circuit constants R₁, R₂, R₃, and C1 (recall ω_n = 2πf_n):

G(s)H(s) = 2ζωn/s + ωn²/s² (standard-form)

= K_ϕF(s)K_oK_n (circuit-constant)

= K_ϕF(s)K_v/sN

= {K_ϕ[(sτ2 + 1)/sτ1]Kv}/sN

= [(K_ϕK_vτ₂)/(Nτ₁)]/s + [(K_ϕKv)/(Nτ₁)]/s²

where:

• F(s) = (sτ₂ + 1)/sτ₁
• τ₁ = R₁C₁
• τ₂ = R₃R₁C₁/2R₂

which we plug into the circuit-constant OL transfer function to obtain the desired relations:

ω_n = (K_ϕK_v/Nτ₁)0.5 = (K_ϕK_v/NR₁C₁)^0.5

ζ = (τ₂/2)(K_ϕK_v/Nτ₁)^0.5

= (R₃R₁/4R₂)(K_ϕK_vC₁/NR₁)^0.5

= ω_nτ₂/2

= ω_nR₃R₁C₁/4R₂

7. Solve for (calculate) initial values of circuit constants R₁, R₂, R₃, and C₁ as functions of standard parameters wn and z, and calculate any other quantities of interest:

τ₁ = K_ϕK_v/ω_n²N

τ₂ = 2ζ/ω_n = 2ζ(Nτ₁/K_ϕK_v)^0.5

R₁ = K_ϕK_v/ω_n²NC₁

R₂ = ω_nR₃R₁C₁/4ζ = (R₃/4ζ)(K_ϕK_vR₁C₁/N)^0.5

C₁ = K_ϕK_v/ω_n²NR₁

Note that R₁, R₂, R₃, and C₁ aren’t uniquely determined, so an absolute selection must be made for two of these values, usually C₁ and R₃. Select C₁ and R₃, then calculate R₁ and R₂:

C₁ = 200 pF, R₃ = 51 Ω_, R₁ = 513.5 Ω (std 5% value 510 Ω), R₂ = 112.6 Ω (std 5% value 110 Ω).

8. Model PLL and simulate performance using a general frequency-domain modeling/simulation tool:

• Genesys, from Keysight Technologies - PathWave Design Division, was used in this case. Adjust OL gain and initial circuit values in model as needed for proper loop dynamics performance from simulations - due to unavoidable discrepancies that usually arise between initial circuit values and adjusted circuit values in model.

9. Build and test EDM unit:

• Using model adjusted circuit values, build and test the EDM unit. Adjust EDM circuit values as needed for proper loop dynamics performance from EDM, due to unavoidable discrepancies that usually will arise between simulated performance and actual EDM performance. The final EDM adjusted circuit values turned out to be:

C₁ = 510 pF, R₃ = 51 Ω (unchanged - proportional amplifier load), R₁ = 1,000 Ω, R₂ = 220 Ω

10. Adjust model OL gain as needed for agreement between model and EDM unit:

• This is best done by adjusting the value of R4 in parallel with the PFD gain control (Fig. 3. again).

These were the design steps used for the PLL and, hence, our single-loop PLL synthesizer. Also shown in Figure 3 are the PFD (voltage output) gain control block, the 1^st Order dual-path active PI loop filter circuit, the PFD reference / sub-harmonic filter block, and the aided acquisition (window steering) block.

The PFD gain control is included to compensate for the variation in effective K_v of 5.4 dB (20 Log (1,635 MHz / 875 MHz)) across the operating band. It consists of a switched resistive voltage divider across the PFD up/down outputs providing approximately 0 to −7.5 dB of adjustment in 16 steps of 0.5 dB. The 1st Order dual-path active PI loop filter has a transfer function zero or transition point of 300 kHz, which is where the transition from the integral (op amp) amplifier to the proportional (differential) amplifier occurs.

The PFD reference / sub-harmonic filter is an LC band-stop type and consists of a 100-MHz full transform band-stop, a 200-MHz single-resonator trap, and a 300-MHz single-resonator trap. The 400-MHz reference should be very well filtered by the loop filter. It was found experimentally that this was indeed the case, so no additional filtering was needed for the 400 MHz reference.

The X4 internal multiplier actually consists of two X2 multipliers because the VCO has its signal path split into two separate signal paths after the first X2 multiplier, each maintaining equal fractional BWs, to be able to properly filter the VCO harmonic spurious. The aided acquisition (window steering) circuit confines the VCO to remain within the operating BW of the PFD and the lock-in range of the PLL.

The above information will be used in the upcoming Part 3, where we model and simulate the example synthesizer PLL section loop dynamics and measure its critical characteristics, which demonstrates the excellent performance achieved using the technique.

Acknowledgements

This paper represents the coalescence, organization, and technical writing by the author of the work done by a number of top technical professionals with expertise in frequency synthesizers, radio/radar, and communications systems. It especially represents the work done by Ben Nardi staff scientist and subject-matter expert in these areas who initiated the synthesizer concept and original design, and who produced a prototype unit.

It was a pleasure for the author to have worked with and to have exchanged ideas with these professionals and, particularly, Mr. Nardi. It allowed the author to assume leadership of the synthesizer with his own team, thereby adding his own ideas and developing it to its final production condition. This gave the author the ability to write this paper and, in doing so, further solidified and expanded his knowledge of the subject of PLLs and indirect (PLL) synthesizers.

References

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3. P. V. Brennan, Phase-Locked Loops: Principles and Practice, McGraw-Hill, New York, 1996.

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5. B. Nardi, personal communication, Gaithersburg, MD, 2008.

6. A. Harney, “Designing High-Performance Phase-Locked Loops with High-Voltage VCOs,” Analog Dialogue 43-12, Analog Devices, December 2009.

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11.  S. A. Sedra and K. C. Smith, Microelectronic Circuits, 6^th ed., Oxford University Press, New York, 2010.

12. “Control System Development Using Dynamic Signal Analyzers,” Application Note 243-2, Hewlett-Packard Co., Palo Alto, CA, 1984.

13. Motorola Communications Device Data, Data Book, DL136/D, REV 4, Phoenix, AZ, 1995.

14. F. C. Weist, “Phase Locked Loop Basics for Frequency Synthesizer Applications,” 2010, short course presentation (© 2010 by Frederick Weist), Clarksburg, MD, 2010.

15. “What Frequency Bands Will Roll Out the Carpet for an Official 5G Standard?,” Microwaves & RF magazine, Vol. 56, No. 6, June 2017, p. 20.

16. “Navigating the 5G NR Standards,” Microwave Journal, Vol. 61, No. 12, December 2018, p. 72.

17. S. Pongratz, “6G and The Long RF Journey Ahead,” Microwave Journal, ePublishing Online Article, February 2024.

18. C.-X. Wang et al., “On the Road to 6G: Visions, Requirements, Key Technologies and Testbeds,” IEEE Communications Surveys & Tutorials, Vol. 25, No. 2, Second Quarter 2023, pp. 905 – 974.

19. F.M. Gardner, Phaselock Techniques, 3rd ed., Wiley, Hoboken, NJ, 2005.

20. R. E. Best, Phase-Locked Loops, Design, Simulation and Applications, 6th ed., McGraw-Hill, New York, 2007.

21. P. V. Brennan, Phase-Locked Loops: Principles and Practice, McGraw-Hill, New York, 1996.

22. E. Drucker, “Phase Lock Loops and Frequency Synthesis for Wireless Engineers,” 1997, Frequency Synthesis & Phase-Locked Loop Design, three-day short course, Besser Associates, Mountain View, CA, 1999.

23. B. Nardi, personal communication, Gaithersburg, MD, 2008.

24. A. Harney, “Designing High-Performance Phase-Locked Loops with High-Voltage VCOs,” Analog Dialogue 43-12, Analog Devices, December 2009.

25. R. C. Dorf and R. H. Bishop, Modern Control Systems, 9^th ed., Prentice-Hall, Upper Saddle River, NJ, 2001.

26. W. J. Palm, III, Modeling, Analysis, and Control of Dynamic Systems, 2nd ed., Wiley, New York, 2000.

27. G. Ellis, Control System Design Guide, 2nd ed., Academic Press, San Diego, 2000

28. W. H. Hayward, Introduction to Radio Frequency Design, Prentice-Hall, Englewood Cliffs, NJ, 1982.

29.  S. A. Sedra and K. C. Smith, Microelectronic Circuits, 6^th ed., Oxford University Press, New York, 2010.

30. “Control System Development Using Dynamic Signal Analyzers,” Application Note 243-2, Hewlett-Packard Co., Palo Alto, CA, 1984.

31. Motorola Communications Device Data, Data Book, DL136/D, REV 4, Phoenix, AZ, 1995.

32. F. C. Weist, “Phase Locked Loop Basics for Frequency Synthesizer Applications,” 2010, short course presentation (© 2010 by Frederick Weist), Clarksburg, MD, 2010.

33.  “What Frequency Bands Will Roll Out the Carpet for an Official 5G Standard?,” Microwaves & RF magazine, Vol. 56, No. 6, June 2017, p. 20.

34. “Navigating the 5G NR Standards,” Microwave Journal, Vol. 61, No. 12, December 2018, p. 72

35. S. Pongratz, “6G and The Long RF Journey Ahead”, Microwave Journal, ePublishing Online Article, February 2024.

36. C.-X. Wang et al., “On the Road to 6G: Visions, Requirements, Key Technologies and Testbeds,” IEEE Communications Surveys & Tutorials, Vol. 25, No. 2, Second Quarter 2023, pp. 905 – 974.