Clock Domain Crossing and Synchronizers (Part 2): Best Practices (Download)
As chip designs grow in complexity and face tighter power constraints, depending on a single clock domain is no longer practical. Instead, most modern chips incorporate as many as dozens or even hundreds of asynchronous clocks.
However, transferring data between two asynchronous domains can cause clock domain crossing (CDC) challenges. One of the most critical issues is metastability, which may disrupt logic and potentially cause system failure. To reduce the risk of metastability, chip designers chain together flip-flops into synchronizers. These components make sure signals are stable before they continue through the rest of the logic.