Anaheim, CA. Andrew B. Kahng delivered a keynote address titled “Modeling the Future of Semiconductors (AND TEST!)” at the International Test Conference here Wednesday. Kahng, a professor at the University of California at San Diego, commented on the semiconductor products that will drive manufacturing and test technology over the next 10 to 15 years, with an emphasis on heterogeneous integration, “More Moore,” and “More than Moore” scaling.
His focus was ITRS 2.0, a version of the semiconductor industry’s International Technology Roadmap for Semiconductors. He described ITRS as an IC-centric roadmap driven by high-volume custom IC products, MPUs, DRAM, ASICs, and flash memory, with metrics related to pitch scaling, lithography, cost of test, transistor count, and on-chip frequency. ITRS 1.0, he said, was bottoms-up, with a focus on what can be made. In contrast, ITRS 2.0 is top-down applications-driven, with a focus on what will be made, with markets in the driver’s seat.
He cited seven areas of emphasis that will be important through 2020 and beyond:
- system integration,
- outside system connectivity, both physical and optical,
- heterogeneous integration of components whose performance will be greater than that of the sum of the individual parts,
- heterogeneous components such as sensors and MEMS that don’t scale well,
- beyond CMOS (memristors, for example),
- “More Moore,” and
Kahng also cited three key applications areas:
- mobility/smartphone,
- datacenter/microserver, and
- Internet of Things/smart object.
The ITRS 2.0 process, he said, will involve gathering and analyzing data and identifying key metrics such as die-to-die wires per dollar. Also involved will be exploration of models, software, system architectures, energy, and the thermal limits of computation. It will be necessary, he added, to infer challenges and potential solutions—exposing red bricks that require early investment to solve
The smartphone market, he said, will be driven by computer vision and 3D displays. It will involve mining of user behavior to improve the human-computer interfces as well as better MEMS integration in single package.
All aspects will implicate packaging and test with respect to testability overhead, cost of manufacturing test, and yield loss due to suboptimal test.
He noted that in the cellphone market, integration and dis-integration proceeds in waves. The advent of the application processor in 2007, for example, resulted in fewer chips per phone. But the proliferating number of sensors and RF capabilities is leading to a near-term growth in the number of chips per phone. After 2020, though, he sees more functions merging into a single die.
Kahng next turned his attention to the datacenter, which will be central to future of the cloud, with servers, storage, and network fabric driving semiconductor technology. Latency and bandwidth will be dominant metrics, and he said that networking must become optical and that nonvolatile memory will overtake mechanical disks. Electro-optical integration may require compound semiconductors. In addition, GFLOPS/W must grow 10-fold in five years.
Of the three application areas driving ITRS 2.0, he said, IoT is interesting but the least well defined, involving MCUs, sensors, connectivity, batteries, energy harvesting, and security. Power conversion and regulation, he said, wastes enormous amounts of energy. The technology may be driven in the short term by “reverse Moore”—using mature process nodes to operate at extremely low power. But, he said, he expects IoT devices to be fabricated at leading-edge nodes in a few years. And the IoT will also see tension between integration and dis-integration.
In conclusion, Kahng told ITC attendees, “Your involvement is welcome.”
