Geneva, Switzerland: The entire NAND flash memory family developed by STMicroelectronics is now available in 70nm process technology. The high-density memory chips are designed to provide mass data storage in a range of computing and consumer applications— digital cameras, PDAs, GPS navigation systems, flash cards and USB drives, printers, set-top boxes (STBs), digital TV sets, car multimedia systems, and mobile handsets with multimedia features.
All of the devices provide fast data throughput and erase capability. The Address lines and Data Input/Output signals of all family members are multiplexed onto an 8 or 16bit bus. This reduces pin count and allows the use of a modular NAND interface, which enables systems to be adapted for higher (or lower) density devices without changing the device footprint.
ST’s software tool chain enables the fast development of products that use the new memory chips, and can help to extend their useful life. Tools include Error Correction Code (ECC) software; Bad Block Management (BBM) to recognize and replace a block that fails an Erase or Program operation by copying its data to a valid block; Wear Leveling algorithms to optimise aging of the device by distributing Erase and Program operations among all blocks; File System OS Native reference software; and hardware simulation models.
Memory is organised into blocks that can be read and programmed by page. Each page contains a Spare Area, whose bytes are typically used for Error Correction Codes, software flags, or Bad Block identification.
A Copy Back Program mode makes it possible for data stored in one page to be programmed directly into another without having to resort to external buffering. A Block Erase command with an erase time of 2ms is provided. Each block is specified for 100,000 Program and Erase cycles, as well as 10- year data retention.
