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Siemens Adds AI to Help Boost Productivity of Chip Engineers

Feb. 23, 2023
The intent behind the new Questa Verification IQ platform is to help speed up the chip design process.

This article is part of the TechXchange: Addressing Chip Verification Challenges.

According to Siemens EDA, its latest software platform, partly powered by machine learning (ML), improves the productivity of chip engineers, reducing the amount of time and resources they invest in verification.

The company, one of the leading players in the world of EDA software tools, said the platform, known as Questa Verification IQ, helps engineers make sense of the vast amounts of data that’s amassed during verification.

The software serves as a sort of central portal for all of the data stemming from Siemens verification engines, in many cases using ML to help pinpoint the root cause of problems in chip designs and highlight areas of a chip that require more verification. It’s designed to present these “data-driven” insights in such a way that fosters collaboration among engineers, enabling them to close out complex chip designs faster.

“Data is transforming the world,” said Darron May, product manager in the design verification technology division of Siemens. “We need to get onboard and make sure we’re using it” to help hardware verification.

The company claims that it’s taking Arm and other early customers significantly less time—20% to 50% in the cases it highlighted in a presentation—to reach design closure using Questa Verification IQ.

Design, Then Verify

Developing a modern chip today is a complex three-dimensional design problem that can take months to years and cost hundreds of millions of dollars, with the most advanced systems-on-chips (SoCs) cramming billions of transistors in squares as small as a fingernail. As a result, it’s impossible for even the most skilled engineers to account for every single detail of a design without using chip-design software from the likes of Siemens.

Modern chips are so complex that it’s becoming a serious challenge to identify flaws or other weaknesses during the verification process prior to mass production. As a result, it’s also taking longer for engineers to reach a point—called “design closure”—when they know enough of the right kind of verification has been done to make sure everything works as intended.

Other companies such as Cadence and Synopsys also are adding artificial intelligence (AI) to their semiconductor design tools to help engineers achieve better results faster while balancing tradeoffs on speed, power efficiency, and cost.

But as Siemens and its peers point out, these tools are not going to replace chip designers anytime soon. Instead, they promise to augment human resources when dealing with relatively menial and tedious tasks, freeing up skilled engineers to focus on innovation.

Verification is a prime candidate for AI, in part because of how time-consuming it is to confirm that everything works on the chip. Siemens estimates that verification accounts for more than 70% of the total development cycle for logic chips.

AI Under the Hood

As these difficulties become even more acute, Siemens hopes to lend a helping hand with Questa Verification IQ.

The platform brings together coverage data from the formal verification and simulation engines within Siemens’ Questa platform, OneSpin software, Symphony platform for analog and mixed-signal simulation, and Veloce hardware for emulation and prototyping. From there, customers can select several different apps, some powered by ML and others by traditional data analytics, to assess the data.

One of the most important tools in the toolbox is “Regression Navigator,” which helps engineers drill down into the results of every test in every regression over the lifecycle of the design and speed up turnaround times. The software uses a type of AI called reinforcement learning to more quickly root-cause issues with a chip design.

In reinforcement learning, the AI is given a job to do without many instructions on how to accomplish it. The AI is rewarded (virtually) when it gets closer to completing the task—in this case, figuring out why the chip design failed a test. Alternatively, when the AI makes a mistake, a virtual penalty is given. By paying attention to the occasions when it’s rewarded and punished, the software can figure out the best way to reach the objective.

Another part of the package is what Siemens refers to as “Coverage Analyzer.” While it’s not intended to indicate the quality of the final design, test coverage is critical for identifying what areas of the chip have—or have not—been tested during the verification process. The company said that this tool uses unsupervised learning under the hood to help identify the parts of the chip design that have yet to be sufficiently tested. 

Questa Verification IQ turns these insights into heat maps and other visual aids that can help everyone working on a project, from rank-and-file engineers to management, to pinpoint where more work is required.

Another tool called “Verification Insight” extracts a wide range of different metrics from the data and displays them on a custom dashboard to show where things stand in the overall verification process, said May. Knowing the status of the verification process is critical to planning, execution, and the quality of chips.

Waste Not, Want Not

One problem Siemens is trying to solve with the new platform is that many customers don’t know how to harness all of the data generated over the course of a chip design and make sure it’s not wasted after a project ends.

What stands out about Questa Verification IQ is that it’s integrated with Siemens’ “Polarion” product lifecycle management (PLM) platform to capture the data from every engine run across a project lifecycle.

Polarion helps manage everything from requirements and coding to testing and release management during the design and verification processes. One of the advantages of this is traceability, which is needed in the design stage so that a product meets functional-safety or security-related standards, said Siemens.

Questa Verification IQ can be accessed via a web browser, allowing everyone involved in a project to get on the same page by simply sharing URLs. This should help engineers located in different offices around the world (or those still working from home) to collaborate and share real-time status updates with each other. The platform runs in public or hybrid-cloud configurations—or on-premises data centers.

Siemens plans to add more AI-powered apps to the platform in the future to leverage the data at its disposal.

Read more articles in the TechXchange: Addressing Chip Verification Challenges.

About the Author

James Morra | Senior Staff Editor

James Morra is a senior staff editor for Electronic Design, where he covers the semiconductor industry and new technology trends. He also reports on the business behind electrical engineering, including the electronics supply chain. He joined Electronic Design in 2015 and is based in Chicago, Illinois.

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