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  • Addressing Chip Verification Challenges

    Integrated circuits go through detailed verification before ever making a real chip, allowing developers to be confident that the chip will work once it's produced.

    More content from Addressing Chip Verification Challenges

    Siemens EDA
    Siemens Questa Iq Promo Web
    The intent behind the new Questa Verification IQ platform is to help speed up the chip design process.
    Feb. 23, 2023
    Socionext
    Promo Fig 6 Fpga Board With Camera Using Mipi Interface
    Managing challenges and risks that accompany a complex SoC design with FPGA prototyping and verification is critical in reducing or eliminating product delays and associated costs...
    Nov. 4, 2022
    Dashark, Dreamstime
    Wafer Stock Promo
    The new AI-powered Verisium platform from Cadence helps chipmakers identify problem areas in designs faster.
    Oct. 11, 2022
    G00b | Dreamstime.com
    Silicon Processor Die Promo
    Today’s high-performance, power-hungry applications require a new approach to power verification. Emulating power pre-silicon will save weeks of simulation experimentation, delivering...
    Dec. 8, 2021
    11myths Promo
    Creation of a specification for a semiconductor can be time-consuming and costly, especially if the project marches on with continued refinements. Automating the process is the...
    June 16, 2021
    11myths Promo
    Verification expert Dr. Lauro Rizzatti debunks the myths surrounding the two tool classes of HAV platforms—hardware emulators and FPGA prototypes.
    June 7, 2021
    Promo Mentor New
    A transformational change in the design and verification of electronics for autonomous vehicles will create a competitive advantage for automotive OEMs.
    July 29, 2020
    Jesd204 8 Prom Onew
    Designing with a high-speed interface like JESD204B always brings new challenges. This article discusses the specification, reviews the tests needed to validate JESD204B devices...
    July 13, 2020
    11mythsVerification_promo.jpg
    To a savvy chip design verification engineer, VIP is much more than a catchy acronym. Designers understand that verification intellectual property is a mainstay of the verification...
    Dec. 11, 2019
    11 Myths About Formal Verification
    Formal verification is used by almost every chip development and verification group, though myths about it persist and may deter engineers who could benefit from its value.
    Oct. 11, 2018
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    FastSPICE offers more speed and the ability to simulate larger circuits than SPICE, but it has limitations, opening the door to the emerging GigaSpice simulation alternative. ...
    March 8, 2016
    Image
    Today's coverage technology exists today to create scenario models; automatically generate coverage goals; automatically generate test cases to hit those goals; and combine...
    Dec. 8, 2014
    Image
    Automating the handwritten C tests that run on the SoC’s embedded processors will increase team productivity and foster reuse throughout the project.
    April 17, 2014