Arteris Bridges the Gap Between Hardware and Software with New EDA Tool

In today’s semiconductor landscape, scale is becoming a bigger battleground—not only for chipmakers, but increasingly for hyperscalers, cloud giants, and other systems companies, too. They're all racing to roll out a new class of ultra-large systems-on-chips (SoCs), cramming tens of billions of transistors and incorporating a wide range of IP blocks to handle computationally heavy workloads, such as AI training and inferencing.

In many cases, these chips are breaking out of the limits of monolithic chips, integrating heterogeneous dies or "chiplets" using 2.5D and 3D packaging technologies.

But the real value of the hardware ultimately hinges on the software stack that runs on top of it. The hardware-software interface, or HSI, plays a central role in a modern chip design, linking the physical hardware and the software and firmware that executes on top of it.

Bridging the gap, however, is becoming a bigger challenge, said K. Charles Janac, the CEO of Arteris. "Effectively addressing hardware and software integration has become quite a challenge for SoC teams, particularly given added complexity and growing chip sizes driven by the infusion of AI logic."

Arteris introduced its latest electronic design software, Magillem Registers, to cut through the complexity. The company said the EDA tool automates the hardware-software integration process, reducing the development time by up to 35% compared to existing solutions. By bringing up to 3X faster performance and 5X more capacity for larger chip designs, Arteris explained that it can help engineers quickly develop chips and chiplets ranging from IoT devices to complex AI multi-die SoCs for data centers.

Magillem Registers can also zoom into the underlying chip designs to pinpoint potential issues, reducing the risk of costly silicon respins, saving companies substantial time and expense during product development.

Arteris—also one of the leading players in network-on-chip (NoC) technology for SoCs—said the new tool enables engineers to focus on innovation by tackling many of the more tedious facets of chip design. According to the company, it allows chip companies to reallocate their engineering resources, saving one to two dedicated engineers per project. The "latest release of Magillem Registers ensures that SoC engineering productivity is maximized, and project risks are significantly reduced," said Janac.

Understanding the Role of the HSI in Chip Design

Fundamentally, the HSI sets the ground rules for how hardware and software interact. It facilitates communication between processing cores, memory, peripherals, and other hardware components, as well as the software application running on top of it all.

Specifically, the software interacts with hardware registers, which are memory locations in the SoC that control hardware functions. One of the primary roles of the HSI is specifying how software responds to hardware events and handles interrupts. Furthermore, it determines how software can access memory inside the chip—also called memory mapping. A memory map is the bridge between the SoC and the firmware and software executed on top of it.

Additionally, the HSI is responsible for managing the different power states inside the processor and the physical buses, such as AXI or AMBA, used for communication between hardware components in the SoC.

However, stitching together the hardware and software interface is becoming more challenging in the era of AI superchips such as NVIDIA's Blackwell and AMD's Instinct GPUs, turning it into yet another potential weak link in the chip design process.

Arteris said more than 70% of first-time prototypes today must be refabricated due to defects or performance issues uncovered during testing. Designing a high-performance SoC is already expensive and time-consuming, but respins can add tens of millions of dollars in additional costs on top of the product delays.

By delivering up to 3X faster performance, Arteris said Magillem Registers are designed to handle these extremely intricate chip designs while reducing development times—one of the keys to keeping costs down.

The latest generation of Magillem Registers is all about speed and scalability. The tool can process up to 5 million hardware registers in a matter of minutes, allowing engineers to handle highly complex chip designs. It also compiles smaller batches of 100,000 registers in seconds, reducing bottlenecks during development. The tool is compatible with the CAD, CAM, and CAE ecosystem, which is important as chip designers collaborate more closely with system and software engineers early in the design cycle.

According to Arteris, the upgraded the software is able to handle 5X larger chip designs. It has the ability to scale up from small to large multi-die chip designs, which can contain several million control registers each.

Magillem Registers: Streamlining the Hardware-Software Interface

As chips grow increasingly complex, so too does the challenge of getting hardware and software to play nice together. Designing the connections where silicon meets software isn't a solo act. It takes a coordinated effort by chip architects, hardware designers, firmware developers, and verification engineers, all speaking different technical dialects (see figure).

Arteris said Magillem Registers gives them a single, unified system for managing internal maps and hardware registers to keep chips running optimally.

The tool supports a wide range of semiconductor design standards, including IP-XACT and SystemRDL 2.0, the latest revision of the Accellera SystemRDL specification, to improve hardware-software integration.

Figure 1. Arteris said Magellim Registers gives engineers a single, unified system for managing internal maps and hardware registers in complex SoCs and FPGAs.

Arteris said Magellim Registers can automatically output everything from the RTL of the chip design to the system memory maps and firmware headers. By delivering what Arteris called a "single source of truth" for specifications, the tool helps mitigate inconsistencies that arise from different engineers independently specifying, documenting, implementing, and verifying SoC address maps. This approach boosts productivity by promoting efficient IP reuse and ensuring consistency across design teams.

Arteris said it can also be paired with its Magillem Connectivity software to help verify system memory map accessibility and confirm register visibility, removing potential integration pain points early in the chip design process.

Arteris said it can also output SystemVerilog, a hardware description and hardware verification language widely used to design, simulate, test, and implement modern chips. This helps simplify the validation and verification phases of the chip design process, streamlining testing efficiency on very large-scale chip designs. This assists engineers in moving from design specification to implementation, Arteris said.

To pinpoint potential issues further ahead of time, Arteris said Magillem Registers also runs more than 1,000 functional, behavioral, syntactic, and semantic error checks, eliminating costly design mistakes and debugging delays. That helps ensure high-quality output, validating third-party IPs, in-house IPs, and overall system integration to significantly reduce the risk of silicon failure, the company pointed out.

The software also features customizable templates. That makes it easier to reuse proven designs instead of requiring engineers to start over from scratch with every new generation of a chip, Arteris pointed out.

Already adopted in sectors such as automotive and data centers, Magillem Registers is being positioned to handle the demands of AI accelerators and large heterogeneous multi-die chips, where complexity and integration risk are particularly acute.