Physically Aware Network-on-Chip Streamlines SoC Design Cycle

Feb. 22, 2023

The NoC IP configuration tool developed by Arteris IP is designed to optimize layouts while cutting design time.

This video is part of TechXchange Talks.

Arteris IP has released FlexNoC 5, a network-on-chip (NoC) IP configuration tool, designed to improve system-on-chip (SoC) designs and streamline the design cycle. I spoke with Arteris IP's VP of Product Development, Andy Nightingale, about the company's physically aware NoC IP (see video above). The system is designed to provide an optimized, working NoC layout while significantly reducing the design-cycle time.

A NoC is a central component in SoCs these days, as they typically contain multiple cores, accelerators, memory blocks, and interfaces that need to communicate with each other. Timing and design challenges for these blocks is often easier than the NoC because they don't have to span the chip, which continues to get larger as more components are included. The challenge was automating the NoC layout and verification process (Fig. 1).

1. Conventional network-on-chip (NoC) configuration is done manually, and it can take many iterations.

A typical design incorporating a NoC will take weeks to complete (Fig. 2). A significant amount of time is devoted to the manual changes to constraints during place and route (P&R) that are needed to create a working and optimized design. The actual synthesis is accomplished using automated tools, but the co-optimization has been done manually in the past since the designer understands the physical layout and constraints.

2. Place-and-route (P&R) guidance requires multiple iterations to provide workable and optimized layouts.

One of the many tasks involved in the co-optimization process is the design of the pipeline stages. That's because the timing of the NoC is spread across the SoC, and that distance and the time it takes for signals to move across it is significant (Fig. 3). The task isn't necessarily straightforward and some trial and error comes into play, especially when the system's other physical constraints enter the mix.

3. One timing challenge involves where and how many pipeline stages are needed to meet timing, temperature, and performance requirements.

The FlexNoC 5 iteration understands the physical nature of the chip and automates the time details, such as pipeline insertion (Fig. 4). This results in fewer co-optimization iterations and simplifies the designer's role. It also can cut the amount of time required by a factor of five or more.

4. FlexNoC 5 can significantly reduce the time to develop a working, optimized layout.

Reducing turnaround time is a key to improving time-to-market. FlexNoC 5 accomplishes this goal while improving the resulting SoC NoC design, enabling developers to focus on other areas of the chip.

Check out more videos in TechXchange Talks.