Lots of Chip Designing on Tap: From Chiplets to Systems

April 23, 2025
Find out how chip packaging and chiplets will deliver more AI acceleration in the data center.

What you’ll learn:

  • How chiplets are addressing AI in the data center.
  • Chiplet integration styles.
  • Chiplet technology trends.

 

Artificial-intelligence and machine-learning (AI/ML) applications are pushing the performance envelope to the point where chips can’t get any larger on a single die. Enter chiplets.

Chiplets can bring together different die technologies together in a single package to address AI/ML applications (see figure). This is already being done but in a proprietary fashion by large OEMs like NVIDIA. However, standards like UCIe will enable others to provide and utilize chiplets.

Dr. Jawad Nasrullah, CEO at Palo Alto Electron, gave a presentation (watch the video above) that takes a look at why we need chiplets, where we are now, and what the biggest challenge will be for designers. Watch the video to get the answers to those all-important questions.

>>Check out this TechXchange for similar articles and videos

Mixing dies, interposers, and designs to fabricate new solutions.
About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

I still get a hand on software and electronic hardware. Some of this can be found on our Kit Close-Up video series. You can also see me on many of our TechXchange Talk videos. I am interested in a range of projects from robotics to artificial intelligence. 

About the Author

Dr. Jawad Nasrullah | CEO, Palo Alto Electron

Dr. Jawad Nasrullah is the CEO of Palo Alto Electron Inc., leading research and development in heterogeneous integrated circuits and 3D ICs for high-performance computing. He co-leads the Open Chiplet Economy initiative at the Open Compute Project Foundation.

Previously, he served as President, CTO, and Co-Founder of zGlue, where he developed a platform for chiplet integration and a marketplace for their distribution. Before zGlue, he held engineering roles at Intel Sun Microsystems, Transmeta Corp., and Samsung. Dr. Nasrullah holds a Ph.D. in Electrical Engineering from Stanford University and is an inventor with numerous publications and patents.

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