The UCIe Consortium’s Universal Chiplet Interconnect Express (UCIe) specification is in its second iteration. It targets designs built around chiplets providing the interconnect between die. The die-to-die standard defines a complete stack from the physical layer on up (Fig. 1).
UCIe has quite a following, including Synopsys, which provides IP as well as design tools that support UCIe. I talked with Mick Posner, Vice President of Product Management at Synopsys, about UCIe and what it involves from design to testing (watch the video above).
UCIe supports a multi-vendor ecosystem for system-on-chip (SoC) designs using chiplets. It complements other die-to-die interconnects like the Open Compute Project’s bunch-of-wires (BOW) specification.
The UCIe 2.0 specification added features like optional manageability and the UCIe DFx Architecture (UDA). It defines a management fabric within each chiplet to support telemetry, testing, and debug services to provide a unified approach to chip management. The new specification is backward compatible with features like spare link, which allows for continued operation when another link fails (Fig. 2).
