TechXchange: Designing with Chiplets

Mixing dies, interposers, and designs to fabricate new solutions.
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Nov. 5, 2024
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What You'll Learn

  • What are chiplets
  • How chiplets are designed and connected
  • Chiplet packaging
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6914b51cc09d7e2a4359c2fa Designing With Chiplets

This TechXchange collects together content that addresses chiplet technology. 

Related TechXchanges

Check out more topic focused technology that impacts the design and use of chiplets. 

Taking a close look at chip packaging technology including new advances such as chiplets.
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Data centers and cloud data centers employ a lot of hardware and software, much of which is specific to those environments. Designing these systems touches on a range of different...

Chiplet Videos

This videos delve into chiplet technology, use and implementation. 

The Chiplet PHY Designer can model and analyze D2D PHY chiplet systems from transmitter to receiver.
How can chiplets address the ever-increasing compute demands of SoCs and processors?
Cadence's UCIe demo presents key features and interoperability support, and also discusses the future of chiplet technology in high-performance SoCs.
Find out how chip packaging and chiplets will deliver more AI acceleration in the data center.
Objective Analysis’ Jim Handy provides insight into the growth of chiplets.
This superpanel explores the role of chiplets in advancing ever-expanding generative AI technology.
The UCIe Consortium’s Brian Rea gives a short overview of the Universal Chiplet Interconnect Express.
Arm’s Chiplet System Architecture, which addresses key chip design challenges, builds on the Neoverse Compute Subsystem and AMBA.
Wrapping up the 2024 Chiplet Summit, this panel session discussed the huge advantages and persistent challenges presented by chiplets.
With the right investments, chiplets can help solve long-standing industry challenges such as increasing costs and supply disruptions, resulting in a world where devices are more...
This webinar is an Electronic Design Member Exclusive Event. Please log in to view the video archive of our panel of EDA experts.
Testing chiplet designs requires an integrated toolset like the BERTs available from Keysight.

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Overview of Chiplets

This section takes a look at what chiplets are and where the technology is headed. 

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Chiplet architectures promise speed and flexibility, but as systems scale, latency, bandwidth efficiency, and coherence determine real performance.
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UCIe 3.0 springs open the door to higher speeds, enhanced link reliability, and smarter system coordination for increasingly complex chiplet packaging needs.
Unlock the future of semiconductor innovation with chiplets — enabling scalable, cost-effective designs and paving the way for a reusable chip marketplace.
With chiplets gaining traction, chip designers face a critical question: When should you step away from a monolithic ASIC? The answer, according to IC-Link by imec, is complicated...
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Learn more about Pike Creek and its potential implications as the first test chip featuring chiplets linked by the UCIe standard.
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When it comes to chiplets, it’s all about packaging technology.
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Jim Handy’s crystal ball reveals trends about many topics, ranging from memory chips to generative AI.
Objective Analysis’ Jim Handy provides insight into the growth of chiplets.

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The Chiplet Ecosystem

These articles take a look at the growing ecosystem for chiplets and related design tools. 

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Chiplets can create custom system-on-chips for designs with better performance and lower power consumption compared to monolithic chips.
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The move to multi-die integration brings both promise and complexity. Scalable interconnects and automation are emerging as key enablers of future designs.
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JEDEC’s HBM4 and the emerging SPHBM4 standard boost bandwidth and expand packaging options, helping AI and HPC systems push past the memory and I/O walls.
The new standard will enable companies to design custom chiplets within a shared interconnect ecosystem.
Arm’s Chiplet System Architecture, which addresses key chip design challenges, builds on the Neoverse Compute Subsystem and AMBA.
Learn more about the motivations behind Cadence’s new Arm-based system chiplet in the latest installment of The Briefing.
Intel’s latest data-center CPU is a prelude to the process and packaging innovations it has in store for 2024.
Explore the main driving forces behind today’s multi-die systems, how they’re becoming the choice system architecture, and how they’re catalyzing the next wave of semiconductor...
The recently announced Universal Chiplet Interconnect Express standard, based on PCIe and CXL, will help simplify chip design.
zGlue’s ChipBuilder Pro lets designers create chips using its 2.5D chiplet Smart Fabric.
TSMC Works With Arm to Chart Future of Chiplets
Intel Adds New Technology to Advanced Packaging Arsenal

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Chiplet Design Tools and Technology

These articles take a look at tools for designing and implementing chiplets.

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Explore Keysight’s Chiplet PHY Designer tool and the game-changing UCIe standard in chip design.
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Design teams are under pressure to integrate more functionality in less time. Structured metadata and automation help manage complexity across multiple abstraction levels.
Learn how Ansys leverages NVIDIA’s Omniverse to unlock the future of 2.5D and 3D multi-die systems.
The company rolled out Calibre 3D Thermal to help deliver fast and accurate die-level thermal analysis of 3D IC designs.

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Chiplet Connectivity

Chips are not standalone items. They require underlying support and connectivity. These articles take a look at this technology and related issues. 

Learn more about the UCIe 2.0 specification and how it could untangle the technical and business challenges holding back the future of chiplets.
The UCIe Consortium’s Brian Rea gives a short overview of the Universal Chiplet Interconnect Express.
Discover how the Universal Memory Interface tackles substrate- and die-level real-estate challenges in chiplet-based design, unlocking performance and scalability.
Intel paired one of its CPUs with an optical compute interconnect (OCI) chiplet.

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Using Chiplets

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The tech integrates 2.5D packaging technology and 3D silicon stacking to usher in the next generation of “superchips” for AI.
The company’s next-gen AI silicon adds more accelerator cores, faster networking, and extra high-bandwidth memory.
The Versal Premium adaptive System-on-Chip (SoC) targets EDA simulation and verification applications.
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Intel’s Agilex 7 with R-Tile support works with PCIe 5.0 and CXL.
Intel Introduces New Way to Stack Chips on Top of Each Other
This silicon interposer fabric lets developers integrate multiple die into a single, compact chip. It is ideal for compact form factors needed for applications like wearable devices...

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About the Author

William G. Wong
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William G. Wong

Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

I still get a hand on software and electronic hardware. Some of this can be found on our Kit Close-Up video series. You can also see me on many of our TechXchange Talk videos. I am interested in a range of projects from robotics to artificial intelligence. 

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