Bridging the Gap to Chiplet Interoperability

Chiplets have emerged as a dominant theme in discussions of next-generation system architectures. The current narrative describes a vision where design teams can mix and match dies from different sources, using standard interfaces and simplified flows to build multi-die systems.

The analogy to off-the-shelf IP components is often cited, with chiplets expected to become as accessible and interoperable as passives or even microcontrollers. However, while compelling, this narrative is still a long way from reality.

The Current Landscape of Chiplet Integration

Chiplets typically fall into two architectural categories: homogeneous scale-out and heterogeneous disaggregation. Homogeneous designs use multiple identical dies within a package to expand performance capacity, while heterogeneous approaches combine functionally distinct dies tailored to specific roles.

Figure 1 illustrates both approaches, where multi-die systems are constructed from repeated compute units or specialized blocks interconnected to form a unified system. These high-level architectural strategies shape how design teams balance scalability, performance, and manufacturing complexity.

While multi-die systems are in production, current implementations are confined to specific use cases. Large companies build chiplets in-house, controlling all design, integration, and packaging aspects. In contrast, smaller companies collaborate with one or two trusted partners, working within tightly coordinated development flows where deliverables are shared before tape-out. These methods result in functional designs but don’t reflect an interoperable environment yet.

Many companies invest in chiplets and related packaging technologies, but enabling true multi-vendor chiplet interoperability is still a significant hurdle. Each vendor typically uses proprietary design tools, verification flows, packaging methods, and interface standards, which makes integrating chiplets from different suppliers a complex task.

Standards such as UCIe are helping at the physical and protocol layers. However, full system-level integration still depends on common address mapping, coherency models, and software alignment.

Chiplets can be integrated across dies, necessitating a custom design tailored to specific requirements. Achieving broader interoperability, where different chiplets can be combined within a single system, would require a standardized design flow that doesn’t yet exist.

Realizing it will depend on continued progress in interface standards, design automation tools, system-level verification, simulation, advanced testing, and industry-wide collaboration. Until then, true plug-and-play interoperability of chiplet technology remains aspirational.

NoC Architectures Bridge Disaggregated Designs

Many integration challenges that currently limit chiplet interoperability are similar to those faced in the earlier adoption of soft and hard IP.

Soft IP is delivered as synthesizable RTL code that can be integrated into various process technologies, making it portable and easy to adapt across different designs. Hard IP is a fixed physical layout optimized for a specific technology node, limiting its reusability and flexibility. Unlike soft IP, hard IP components, such as memory interfaces, have remained difficult to reuse because they must match exact process characteristics.

Chiplets, as physically disaggregated hard IP, extend these challenges. Each die must be compatible with the protocol, power domain, process node, and performance targets. Without unified standards and infrastructure, the design complexity increases significantly.

Many engineers are adapting network-on-chip (NoC) architectures originally developed to manage the integration of IPs within SoCs — and extending them to work across multiple dies. In single-die designs, NoCs enable communication between IP blocks by routing packets based on unique destination addresses. A NoC can be instantiated on each die in multi-die systems, with bridges connecting them.

This architecture allows multiple independent NoCs to appear functionally unified. They preserve register maps and address integrity while accommodating bandwidth, power domain, and configuration differences. Design teams can partition SoCs into multiple dies while maintaining system-level functionality and performance goals.

Disaggregation makes it possible for companies to develop systems that more efficiently meet performance, cost, and compliance requirements. By separating functions such as I/O interfaces, digital logic, and memory control into dedicated dies, each can be implemented in the most suitable process node.

Advanced semiconductor developers already use these strategies. In sectors such as automotive, where reliability and certification are critical, disaggregation supports incremental upgrades to individual chiplets while maintaining compliance across the rest of the system.

Looking Ahead to a Chiplet Ecosystem

The long-term vision is a chiplet ecosystem where teams can select components from different suppliers and integrate them using interoperable standards. Much like today's ability to combine libraries from multiple sources through standardized application programming interfaces (APIs), this model would bring greater flexibility, faster development cycles, and a more modular approach to system design.

However, today’s reality remains rooted in proprietary flows and pre-verified partnerships. While multi-die systems are already in production, especially for major players, their integration depends on controlled development environments and close coordination between trusted vendors.

In the meantime, advances in interconnect, packaging, and NoC abstraction establish the groundwork for future interoperability. For instance, as illustrated in Figure 2, Arteris offers a scalable multi-die connectivity solution that addresses both current needs and emerging chiplet models.

To support chiplet-based system development, this solution spans system IP products for interconnect, coherency, and integration automation. Configurable interconnect solutions supporting coherent and non-coherent communication across multiple dies are available with its FlexNoC and FlexGen. These are complemented with platforms such as Ncore, which delivers high-performance cache-coherent interconnect with distributed hardware-managed coherency for multi-core and multi-die architectures.

The assembly of IPs and chiplets by capturing and managing interfaces, hierarchies, and configuration data compliance can be achieved with a solution such as Arteris’ Magillem Connectivity. In addition, Magillem Registers provides a single source of truth for memory maps and register information, enabling consistent generation of software and verification views. On another front, tools like Magillem Packaging can automate the extraction and formatting of IP and subsystem descriptions to support correct-by-construction integration.

These technologies help streamline design flows and enable scalable, standards-based development of complex multi-die systems.

As the industry moves in this direction, it will be essential to maintain a realistic view. The chiplet model holds great promise, but achieving its full potential will take time.