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Arteris IP

Arteris technology transforms IP blocks into optimized SoCs. Learn more at arteris.com.
595 Millich Dr. Suite 200
Campbell, CA 95008
+1 408 470 7300

More Info on Arteris IP

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Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration technology enables SoC creation success with proven flexibility and ease for a variety of applications and markets including AI, automotive, communications, consumer electronics, enterprise computing, and industrial. Arteris technology ensures higher product performance with lower power consumption and faster time to market, delivering better SoC economics for its global customer base including semiconductor manufacturers, OEMs, hyperscale system houses, semiconductor design houses and other producers of electronic systems.

The Arteris product line is silicon-proven, supporting SoC innovation from creation to integration.

Network-on-Chip IP Products

  • Non-coherent NoC IP, with FlexNoC and FlexWay
  • Cache-coherent NoC IP, with Ncore
  • Last-level Cache, with CodaCache

SoC Integration Products

  • SoC integration with Magillem Connectivity, Magillem Registers, and CSRCompiler

Videos

What’s the Difference Between Soft NoC Tiling and Hard Tiling?
Arteris’s FlexNoC supports soft tiling that’s targeted at AI and multicore chips.
Oct. 25, 2024
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The NoC IP configuration tool developed by Arteris IP is designed to optimize layouts while cutting design time.
Feb. 22, 2023
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Bill Wong and Paul Graykowski discuss Harmony Trace which enables design teams to monitor impacts to requirements of complex SoCs by creating and maintaining traceability between...
April 18, 2022

Articles

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Design teams are under pressure to integrate more functionality in less time. Structured metadata and automation help manage complexity across multiple abstraction levels.
Sept. 24, 2025
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Magillem Registers is all about speeding up the design of hardware-software interfaces in complex, large-scale SoCs.
May 28, 2025
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As SoCs grow in complexity, manual NoC generation is no longer practical. This article highlights how automated NoC generation streamlines interconnect development to improve ...
May 2, 2025
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Arteris’s FlexNoC uses artificial intelligence to create more efficient network-on-chip configurations.
Feb. 25, 2025
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Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache...
June 27, 2024
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How to navigate the complexities of building functional safety into SoC design, including managing IP blocks, CSRs, and adhering to standards like ISO 26262.
May 16, 2024
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The Ncore network-on-chip design tool developed by Arteris delivers ISO 26262 certification.
March 26, 2024
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Register-transfer-level (RTL) verification is a critical component to successful chip design.
Jan. 31, 2024
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Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.
Aug. 23, 2023
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At DAC, Arteris featured its system IP, which includes its network-on-chip interconnect IP and system-on-chip integration automation software to help boost product performance...
July 24, 2023

Additional content from Arteris IP

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Increase system quality and accelerate functional-safety assessments by identifying and fixing the traceability gaps between disparate systems.
March 11, 2022