Securing all of the different layers of a system from the application software down to the operating system and the firmware is key to defending against hackers and other threats. However, the silicon forms the foundation for security. The vulnerabilities there can undercut protections in other parts of the system, and hardware itself is increasingly exposed to malicious inclusions and in-field attacks. Unlike software, hardware can’t be easily patched, making it critical to mitigate attacks before they occur and isolate them when they do.

However, hardware security is becoming much more challenging due to the rising complexity of today’s chip designs. More complexity means more potential vulnerabilities that can be exposed or exploited now and in the future.

High-end processors integrate tens of billions of transistors split across different subsystems and even separate chiplets in the same package, expanding the potential for subtle design flaws that can evolve into security vulnerabilities. At the same time, pinpointing the root cause of a problem is more difficult, too.

To help identify and mitigate potential weaknesses, Arm recently announced that it will expand its adoption of Arteris’ Cycuity Radix hardware security assurance tool in future CPU designs.

Under the expanded agreement, Arm will continue to integrate Arteris’ Cycuity technology into its security assurance process. Arteris said its EDA tool reveals security-relevant relationships between different parts of the design, helping engineers identify potential attack surfaces and verify hardware security across CPU architectures and performance features. By exposing security risks earlier in the design process, it aims to reduce hardware vulnerabilities that are impractical or impossible to fix after silicon is fabricated.

“Semiconductor cybersecurity is rapidly becoming a critical part of securing all our electronic systems, including AI data centers,” said Charles Janac, CEO of Arteris.

Lyndon Fawcett, head of product security at Arm, said it’s building more rigorous security assurance across its CPU portfolio.  Arm integrates Arteris’ technology into the CPU design flow rather than running it as a post-silicon audit.

The process starts with architectural and micro-architectural security risk assessments that identify the critical parts of the design and then evaluate them against known threats to establish a set of goals. By surfacing potential issues early, they can be fixed in the design rather than mitigated later.

Arteris added that its approach is also scalable because the “security properties” developed for one CPU design can be reused across future designs, reducing the effort required to validate new processors.