Andrei Dzemidzenka, Dreamstime

Does This Chip Hold the Future of the Semiconductor Industry?

April 3, 2024
Learn more about Pike Creek and its potential implications as the first test chip featuring chiplets linked by the UCIe standard.

Check out Electronic Design's coverage of DesignCon 2024 and Chiplet Summit 2024.

Today, the movers and shakers of the semiconductor industry are no longer putting all of their transistors in one chip. Instead, they’re pulling apart their largest, most advanced chips into smaller silicon die referred to as chiplets. These can be made on the best process technology for the job and then repackaged to mimic a single monolithic system-on-chip (SoC). By integrating the heterogeneous die in a single package, such “multi-die” systems bring more performance to the table for everything from AI to RF.

For now, these companies can mix and match chiplets made by different foundries, based on varying process nodes, and then bind them all together in a system-in-package (SiP) with any type of advanced packaging. But bringing third-party chiplets into the package poses a challenge, largely due to the lack of a standard die-to-die connection. In that context, the biggest names in the chip business are hoping to fill the gap with a new standard, ushering in a new era of domain-specific accelerators in the process.

Intel and Synopsys are highlighting the possibilities. They joined forces to build what the companies called the world’s first multi-die system with chiplets linked by the Universal Chiplet Interconnect Express (UCIe). UCIe is a proposed die-to-die interface standard that aims to reduce the friction of integrating third-party chiplets. Though it’s intended as a test chip, Synopsys said it shows the companies’ commitment to support an open ecosystem.

While Intel CEO Pat Gelsinger presented the test chip for the first time at the company’s “Innovation” event last year, Synopsys CEO Sassine Ghazi spotlighted it again at his company’s annual conference last month.

The test chip, code-named Pike Creek, is comprised of an Intel UCIe IP chiplet based on the Intel 3 process technology, paired with a Synopsys UCIe IP chiplet, fabricated on TSMC’s 3-nm node. While they use UCIe to interact with each other, the chiplets are physically linked over Intel’s 2.5D advanced packaging technology— Embedded Multi-Die Interconnect Bridge (EMIB). “This is the future of the semiconductor industry: multiple fabs, multiple sets of industry-standard UCIe IP, and modern EDA packaging solutions,” said Ghazi.

UCIe is in its infancy, but Synopsys said the successful pairing mimics the mixing and matching of dies that can occur in multi-die systems, proving that this approach is commercially viable.

Chiplets: The End of the Monolithic Age of Silicon

Several issues are pushing the semiconductor industry out of the monolithic age of the SoC.

As the semiconductor industry falls further behind on Moore’s Law, transistors aren’t scaling as frequently these days. In turn, this limits the amount of logic and memory that can be arranged on a single processor. The other issue is that chips have reached the “reticle limit” of the manufacturing process for modern chips. As a result, it’s virtually impossible to create a single chip larger than 850 square millimeters or so. The reticle is a stencil used to scorch transistors on the surface of the silicon chip, imposing a hard limit on the chip’s footprint.

Once tested and validated, the chiplets are then bonded together on interposers or other types of 2.5D advanced packaging, including TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) and Intel’s EMIB, where the silicon dies are placed beside each other and interact over short physical connections. The other possibility is to use more advanced 3D stacking technologies that can sling signals around the package faster, as if everything is all on the same chip.

By spreading out the processor’s subsystems over several chiplets, chip designers can effectively increase the silicon area, cramming more transistors—thus, more performance—in a package than possible in a single chip.

One of the perks of a multi-die system architecture is that it can consist of dies from different vendors based on different nodes. This provides flexibility in optimizing power, performance, and area (PPA) and in terms of cost. Every chiplet can be fabricated on the process technology that suits it best, reducing complexity. As process technology evolves, the CPU or other chiplets can be upgraded, while others are left alone.

This flexibility also gives companies the ability to adapt to new markets and technological advances, including AI and ML. Mixing and matching heterogeneous dies opens new possibilities for custom silicon, said Manuel Mota, senior product manager for high-speed interface IP at Synopsys, in a blog

The other major advantage is related to cost. By enabling the best process technology to be applied to every die in the package, chiplets help mitigate the expense of manufacturing at more advanced nodes, added Mota.

But the transition from a SoC to a SiP is not without some tradeoffs. Disassembling a single slab of silicon into several smaller heterogeneous dies and then reassembling them in a package is not easy. It presents difficulties when delivering power and dissipating heat from the system. Another issue stems from spreading everything out over more real estate in the package. That forces all of the chips under the hood to communicate over longer distances, which costs power and latency.

On the edge of every slab of silicon is a PHY that enables high-bandwidth connectivity to the heterogeneous die in the package. It’s paired with a controller to interact with them over different protocols, ranging from UCIe to other emerging technologies like the Bunch of Wires (BoW) standard from the Open Compute Project (OCP) and the Extra Short Reach (XSR) standard. Since these die-to-die interconnects move all of the signals between the chiplets, they must be high quality and highly reliable.

Synopsys said its UCIe IP covers both the PHY and controller IP, which is combined with additional IP to verify the die-to-die connectivity in the package. The company noted that the IP is also designed whereby its customers can identify defective dies before they’re plugged into a package.

The Chiplet Economy: Easy Mixing and Matching

For the most part, chip designers use proprietary interconnects and protocols for linking chiplets, which locks them into using IP designed internally or sourced externally before it’s validated and tested. Though they still have the freedom to use any foundry process or packaging technology, adopting third-party chiplets can be more trouble than it’s worth without a standard way to seamlessly connect everything in the same package.

“When one company controls both sides of a link, there are, of course, no concerns about whether each side will work together,” said Mota. “But moving forward, over the next few years, we’ll probably start seeing more companies who prefer not to build both sides, instead choosing to buy components off the market.”

UCIe is emerging as a potential answer to the problem. Introduced in 2022, UCIe is a die-to-die interconnect aimed at creating a standard plug-and-play way for chiplets to communicate with each other in a package.

The companies behind the UCIe standard are aiming to foster a vibrant ecosystem for chiplets that covers processors, memory, connectivity, and everything in between. Using UCIe, chip designers would be able to buy and sell each other’s chiplets and plug them into a package with minimal design and validation. The goal is to make mixing and matching chiplets almost as easy as arranging components on a PCB.

Therefore, chip designers can focus on developing the specific chiplets they need and rely on commoditized technologies for other aspects of the design, creating what industry insiders call a “chiplet economy.”

Other standards are in play, but the UCIe standard is widely considered the de facto standard for die-to-die connectivity because it is supported and adopted by a who’s who of companies in the semiconductor industry—more than 120 in all. Besides Intel, Synopsys, and TSMC, it’s backed by virtually all of the largest chip equipment and EDA suppliers along with top foundries and chip designers like AMD, NVIDIA, and Qualcomm.

While a host of technological advances paved the way for Intel and others to adopt chiplets, open die-to-die interconnects such as UCIe could unlock even more possibilities for the broader industry, said Mota. If UCIe is selected as the industry standard, commercial chips that look like Pike Creek could become a more common sight.

Check out more of our coverage of DesignCon 2024 and Chiplet Summit 2024.

Sponsored Recommendations

TTI Transportation Resource Center

April 8, 2024
From sensors to vehicle electrification, from design to production, on-board and off-board a TTI Transportation Specialist will help you keep moving into the future. TTI has been...

Cornell Dubilier: Push EV Charging to Higher Productivity and Lower Recharge Times

April 8, 2024
Optimized for high efficiency power inverter/converter level 3 EV charging systems, CDE capacitors offer high capacitance values, low inductance (< 5 nH), high ripple current ...

TTI Hybrid & Electric Vehicles Line Card

April 8, 2024
Components for Infrastructure, Connectivity and On-board Systems TTI stocks the premier electrical components that hybrid and electric vehicle manufacturers and suppliers need...

Bourns: Automotive-Grade Components for the Rough Road Ahead

April 8, 2024
The electronics needed for transportation today is getting increasingly more demanding and sophisticated, requiring not only high quality components but those that interface well...


To join the conversation, and become an exclusive member of Electronic Design, create an account today!