Tools for Testing Chiplet-Based Designs

Chiplet technology provides a way of mixing different chip technologies into one solution, but it can be a challenge to test these systems. I spoke with Randy White, Memory Solutions Program Manager at Keysight, about one of the company’s configurations for testing chiplets (watch the video above). The example includes Keysight’s M800 series bit-error-ratio testers (BERTs) and a UXR0334B Infiniium UXR-Series digital oscilloscope.

The M800 series BERTs are built on a five-slot AXIe M9505A chassis (Fig. 1). They can handle connections up to 120 Gbaud supporting physical-layer characterization, validation, and compliance testing. Pulse amplitude modulation 4 (PAM4) and non-return-to-zero (NRZ) formats are supported, with software-selectable NRZ data rates ranging from 2 to 64 Gbit/s for pattern generation and error analysis and PAM4/6/8 data rates from 2 to 120 Gbaud.

Its multichannel capability includes built-in clock, data recovery, and equalization support along with integrated de-emphasis and adjustable intersymbol interference (ISI). It can be used in concert with a variety of protocols, from the chiplet-based UCIe to PCI Express, MIPI, and more.

The M800 is often paired with oscilloscopes like the UXR0334B (Fig. 2). It’s a four-channel real-time oscilloscope with 10-bit analog-to-digital (ADC) converters. Intrinsic jitter is typically under 20 fs.

The capture memory per channel starts at 500 Mpoints/s and ranges up to 2 Gpoints/s. Data rate per channel is 128 GSPS. It supports high-speed serial data analysis (SDA) and clock recovery. On-site self-calibration comes with the optional N2127A calibration module.