Tying Together Chiplets Using Network-on-Chips
What you’ll learn:
- What type of chiplet interconnects are being used now?
- How do network-on-chip (NoC) systems work with chiplet standards like UCIe and BoW?
No one wants to design high-performance chips from the ground up. Taking advantage of IP such as processors and network-on-chips (NoCs) allows designers to quickly configure and build chiplet-based solutions.
I talked with Kent Orthner, Principal Solutions Architect at Baya Systems, about the company’s tools and how NoCs can utilize Universal Chiplet Interconnect Express (UCIe) and the Bunch of Wires (BoW) standards for off-chiplet communication.
Baya Systems provides tools for designing NoCs as well as chiplet-based systems. Typically, many NoCs reside within a system, with some providing cache coherency. The tools support BoW and UCIe so that NoCs on different chiplets can be linked together.
The company's WeaverPro is a tool suite that includes CacheStudio and FabricStudio. CacheStudio is used to design cache-coherent NoCs (Fig. 1). It can simulate workloads to test cache models and provides global optimization support as well as chiplet partitioning tools.
FabricStudio lets developers create on-die, fabric micro-architectures (Fig. 2). These can be dynamically analyzed using a cycle-accurate simulator. The tools support the NeuraScale Scalable Switch Fabric. The system IP solution is designed to provide non-blocking switching between a large number of UALink, Ultra Ethernet, or AMBA ports.
>>Check out more of our 2026 Chiplet Summit coverage
About the Author
William G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
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