What’s New in UCIe 3.0?
What you’ll learn:
- UCIe 3 speeds double the bandwidth over 2.0.
- How UCIe 3.0 expands the number of usage models.
- Power enhancements in the latest standard.
The Universal Chiplet Interconnect Express (UCIe) is designed to connect chiplets together, providing multiple high-speed serial interfaces (see figure). The standard is from the UCIe Consortium, with its latest incarnation being UCIe 3.0. I talked with Brian Rea about the latest UCIe 3.0 standard (watch the video above).
The 3.0 standard doubles the bandwidth compared with the prior version. It expands the number of usage models, and the 3D packaging now allows vertical stacking of chiplets that enhances both performance and power efficiency. The Management Transport Protocol (MTP) supports communication between management entities within a system-in-package (SiP).
Debugging and testing are key to implementing a successful chip package solution. The addition of the UCIe Debug and Test Architecture (UDA) is designed to facilitate this functionality. The architecture can address chiplet-level as well as package-level testing and debugging.
About the Author
William G. WongWilliam G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
I still get a hand on software and electronic hardware. Some of this can be found on our Kit Close-Up video series. You can also see me on many of our TechXchange Talk videos. I am interested in a range of projects from robotics to artificial intelligence.
Brian ReaBrian Rea
Working Group Co-Chair, UCIe Consortium
In addition to working with the UCIe Consortium, Brain works full time at Intel as the Technology Initiative and Ecosystem Enablement Manager. He earned a BSEE from the University of Texas at Austin and an Executive MBA from IW Foster School of Business.