Electronic design software giant Cadence rolled out its Certus Closure Solution, which is intended to optimize chip designs destined to sit at the heart of everything from data-center servers to 5G networks and smartphones.
As the Santa Clara, California-based company explains, the solution’s ability to automate the full chip-level design closure process helps boost engineering productivity by up to 10X compared to existing approaches.
“Closure” refers to the process of optimizing a chip design to meet the power, performance, and area goals of the project, said Brandon Bautz, director of product management in Cadence’s digital and signoff group. It’s closely related to the “signoff” process, in which you check whether the chip design actually meets those goals. He said that in practice, you have to alternate between signoff and closure multiple times to get it right.
Everything that Cadence and other electronic-design-automation (EDA) firms like Ansys, Siemens, and Synopsys do today is driven by the rising complexity of modern chips. Designing a system-on-chip (SoC) is a hugely complex three-dimensional design problem. Packing up to tens of billions of transistors, modern chips have become so intricate that it’s impossible for engineers to build them without assistance from EDA software.
Today, it can take semiconductor engineers several days to accomplish full-chip and subsystem-level design closure, with each pass involving full chip assembly, static timing analysis, plus optimization and signoff. In general, they must repeat these tedious, manual processes many times to dial in the performance, power efficiency, and other aspects of the chip. Consequently, they can spend months closing out the chip design.
Since engineers want to build the best chip that they possibly can, they inevitably spend a long time on the closure process. However, as chips become more complex, it has become a major bottleneck in meeting time-to-market goals.
But according to Chin-Chi Teng, senior vice president and general manager of Cadence’s digital and signoff division, Certus allows customers to get through a full design closure cycle in a matter of hours instead of weeks or months.
Inside Certus
Certus is based on a massively parallel and distributed architecture, giving it more than enough computing capacity to accommodate even the most advanced chip designs, a capability that existing solutions lack, said Cadence.
The other problem Cadence is trying to address with Certus is the lack of integration with other EDA software. As the company sees it, most of the other closure solutions on the market are insufficiently integrated with tools necessary for other phases of the chip design cycle, including placement, routing, and signoff. As a result, engineers are forced to go back and forth between different tools, which seriously slows down the closure process, said Bautz.
Certus uses the same engine as Cadence’s Innovus Implementation System and Tempus Timing Signoff Solution. That gives its customers a fully automated solution for “concurrent optimization and signoff.” Thus, semiconductor firms can close out chip designs without as many tedious iterations, speeding up their time-to-market. The company said Renesas and MaxLinear are among Certus’s early customers.
The solution also offers flexible restore and replacement of only the changed portions of the design. This feature will help speed up final signoff of the chip before it moves into mass production, according to Cadence.
Certus is compatible with cloud environments. But if you decide it’s worth it to amass the huge amount of computing power required to run most EDA workloads, the platform is also suited for execution in traditional, private data centers.
The tool also works with Cadence’s AI-powered Cerebrus Intelligent Chip Explorer solution for physical implementation, giving engineers additional productivity improvements for block-level to full-chip closure.
As many of today’s most advanced chips put chiplets together in a package instead of cramming everything on a single large slab of silicon, the company said Certus also is tightly integrated with its Integrity 3D-IC Solution.