What you’ll learn
- How third-party interconnect IP saves time, lowers risk, and speeds completion.
- NoC is the predominant SoC interconnect strategy.
- NoC IP accommodates multiple interconnect protocols and data widths.
- System IPs enable designers to build high-performance, reliable systems.
Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors, depending on the application. The only way to create designs of this complexity is to employ large numbers of functional blocks called intellectual-property (IP) blocks or IPs.
Many of these blocks embody well-known and standard functions, such as processor cores, communication cores (Ethernet, USB, I2C, SPI, etc.) and peripheral processes. Rather than spend valuable time and resources re-implementing these functions from scratch, SoC design teams acquire these IPs from respected third-party vendors.
Access to robust, tested, and proven IP speeds up the development process and reduces risk. Using third-party IP for common functions frees the SoC design team to focus on their own “secret sauce” IP blocks, which will differentiate their SoC from competitive offerings.
Making SoC Connections with NoCs
An important aspect of any SoC is how the IP blocks will communicate with each other. In the 1990s, it was common to use a bus-based interconnect architecture. By the 2000s, designers adopted crossbar, switch-based interconnect architectures to accommodate the increasing number of IP blocks. In the 2020s, the predominant SoC interconnect strategy involves at least one network-on-chip (NoC) implementation.
When they hear the term “IP,” most SoC designers think of register-transfer-level (RTL) representations at the front end and square or rectangular footprints on the silicon die at the back end. There’s a certain category of SoC IP called “system IP.” Examples of such IP are NoC interconnect, debug and trace components, and memory, cache, interrupt, security, and fault-detection controllers.
System IP enables designers to build high-performance, power-efficient, reliable, and configurable systems for many different applications. NoC system IP spans the entire SoC and interacts with almost every block in the design in some way.
Mitigating SoC Complexity
To lessen the complexity of connectivity in the SoC design, each IP block will typically implement an interconnect protocol. One challenge with purchasing third-party IPs is that, over time, multiple interconnect protocols have been defined and adopted by the SoC industry (OCP, APB, AHB, AXI, STBus, DTL, etc.).
Since an SoC may contain hundreds of IP blocks from various third-party vendors, the interconnect IP must accommodate all of these standard protocols. Furthermore, different IPs may have distinctive data widths and run at varied frequencies.
The interface on an IP is known as a “socket.” A network interface unit (NIU) connects the socket to the NoC. At the transmitting end, an initiator IP’s associated NIU translates its interface and protocol into the internal NoC protocol, including packetizing the data. At the receiving end, an NIU translates the packet in the NoC protocol back into the required target IP interface and protocol.
Multiple packets can be in flight at the same time. The NoC also includes buffers to store data temporarily, switches to guide packets between initiator and target IPs, and pipeline stages to help the physical layout team close timing.
Saving Time and Money with Third-Party NoC IP
Remembering that a NoC is a complex system IP, the SoC development team now has a choice. The designers can create their own interconnect in-house or employ NoC IP from a trusted third-party vendor.
Srivi Dhruvanarayan, VP of hardware engineering at SiMa.ai, has experience creating a NoC in-house at a previous company. In a recent case study, Srivi noted that it took six people working for almost two years to architect, design, and verify an in-house NoC. As a result of that experience, Srivi now uses third-party interconnect IP from Arteris.
There’s much more to a NoC than its NIUs, buffers, and switches. Remembering that NoC interconnects traverse the entire chip, it’s necessary to include pipeline stages to meet timing. Suppose engineers are forced to insert these pipeline stages by hand. They typically overengineer the problem using too many stages, thereby using more silicon die area while increasing latency and power consumption.
The reason for this overengineering is that it takes much time and effort to iterate between the front-end design and the back-end physical layout. With advanced physically aware NoC IP, the product can insert an optimum number of pipeline stages and provide placement suggestions to the downstream physical layout tools. In addition to speeding the physical layout process, it significantly reduces the number of time-consuming back-end to front-end iterations required to achieve timing closure.
Managing today’s complex SoC designs mandates using one or multiple NoCs. A trusted and reliable de facto industry standard, like FlexNoC 5 interconnect IP from Arteris, helps save time, reduce risk, and speed completion time.
At the time of this writing, interconnect IP and system IP from Arteris have been employed in 600+ SoC design starts. As a result, 3+ billion SoCs featuring this IP have shipped in electronic systems worldwide.
In the case of safety-critical designs for which functional safety (FuSa) is a concern, the FlexNoC resilience option complements FlexNoC 5 interconnect IP. The product implements the hardware reliability and FuSa features required for automotive ISO 26262 or IEC 61508 compliance, along with enhanced enterprise SSD endurance.