Digital IC design platform gets a facelift

May 24, 2007
The latest version of Cadence Design System’s Encounter digital IC design platform includes chip optimisation, mixed-signal support for very large 65nm-and-below designs, and diagonal routing using the Encounter X Interconnect Option. It

The latest version of Cadence Design System’s Encounter digital IC design platform includes chip optimisation, mixed-signal support for very large 65nm-and-below designs, and diagonal routing using the Encounter X Interconnect Option. It also offers the previously announced suppor t for Si2’s Common Power Format (CPF) 1.0-enabled low-power design.

A key feature of the latest Encounter platform is support of the Cadence Low-Power Solution, based on Si2’s CPF 1.0 standard. The Low-Power Solution offers a complete flow across logic design, verification, and implementation. CPF is an industry standard form at for specifying power-saving techniques throughout the design process—enabling teams to share and reuse low- power intelligence.

In addition, the new release provides design for manufacturing support, yield optimisation, lithography-aware routing, mixed-signal design using new bus-routing capabilities, and critical path simulation with the Virtuoso UltraSim Full-chip Simulator. The platform also offers new power-aware automatic macro placement capability and support for simultaneous multi-mode and multi-corner timing analysis and optimisation.

“The latest release of Encounter platform represents an important development to the members of STARC, because it addresses, in a comprehensive fashion, the challenges inherent in designing for low power and manufacturing, with high productivity,” says Nubuyuki Nishiguchi, vice president and general manager of STARC. “This integrated, front-to-back approach creates significant value to leading-edge designers.”

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