Cadence Design Systems and Fujitsu Microelectronics America (FMA) have announced that FMA is shipping initial production volumes of a new, complex, structured ASIC using Cadence Encounter IC implementation. Encounter was originally developed for standard ASICs; it provided rapid timing closure with signal integrity for optimal quality-of-silicon (QoS) in the implementation phase of the design flow for FMA's AccelArray family of structured ASICs.
The design incorporates 3.5 million logic gates, 119 instances of 2RW SRAM (40bx512w), 33 instances of register file (40b x 32w) and 12-channel, 3.125G SERDES for high-end servers developed for consumer applications. The design was completed with low, non-recurring costs by using AccelArray Giga Frame.
Fujitsu’s AccelArray Giga platform reduces back-end physical design time such as DFT insertion, power mesh, clock tree synthesis and simultaneous switching output (SSO) analysis – all of which can be time-consuming. The platform offers up to 75Gbps of full-duplex SERDES aggregated bandwidth by incorporating pre-diffused universal G-PHY macro cells.
With SoC Encounter GPS, engineers have an early, accurate view of whether the design will meet its targets and be practicable. Designers can then choose either to complete the final implementation or to revisit the RTL design phase.