IMEC, Riber Team Up to Break 22-nm Geometry Barrier

May 18, 2006
Duo will collaborate to demonstrate how germanium and III-V materials can permit CMOS scaling beyond 22 nm.

It’s a big goal for such a tiny scale. IMEC, the Belgian nanotech research institute, will collaborate with French molecular beam epitaxy (MBE) equipment company Riber to demonstrate how germanium (Ge) and III-V materials will permit CMOS scaling beyond 22 nm. The collaboration also aims to extend the program beyond CMOS and into photonic applications.

Germanium could replace planar silicon, which is unlikely to accommodate the rigorous scaling requirements at geometries smaller than 22 nm. The material also offers higher mobility and lower intrinsic gate delay, making it an excellent candidate for high-performance CMOS devices. Companies then can use existing silicon manufacturing structure instead of building new facilities to produce these devices.

Researchers will use Riber’s ultra-high vacuum MBE cluster system for 200 mm, which includes an III-V compound semiconductor growth chamber and a metal-oxide deposition chamber. This unique cluster will permit the deposition of compound semiconductor layers on germanium-on-insulator (GeOI) or other germanium substrates, as well as high-k dielectrics and metal gates on germanium and III-V materials.

By targeting III-V devices on the same germanium substrates, both parties hope to solve the problems that usually occur with processing germanium nMOS transistors. The process will be based on silicon wafers, enabling manufacturing in a standard silicon process line using advanced CMOS-compatible equipment. Riber’s MBE cluster will help improve the gate stack for MOS devices on germanium and III-V compounds as well.

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