The concept of silicon realization, as defined in the Cadence EDA360 vision paper, represents everything required to produce a system-on-a-chip (SoC) design in silicon.1 Silicon realization addresses the needs of SoC integrators in addition to intellectual-property (IP) creators, as well as recognizes that virtually every SoC today falls into the mixed-signal arena.
Many of these chips handle real-world data, such as audio, video, temperature, and motion. They operate at high-gigahertz speeds. And, they run multiple concurrent applications that require analog and RF components integrated tightly with digital circuitry.
Mixed-signal design isn’t a new methodology, but mixed-signal implementation and verification have become much more challenging in the past few years. A few years ago, “mixed-signal” design usually meant placing a few analog hard macros onto a mostly digital SoC. The move to advanced process nodes, however, has substantially increased analog/mixed-signal content. Today’s SoC designers find themselves integrating extremely large analog, digital, and mixed-signal IP blocks.
SoC Integration Challenges
Most current SoC designs contain analog/mixed-signal blocks such as serializer-deserializer (SERDES) cores, UARTs, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), phase-locked loops (PLLs), and other transceivers. Because analog doesn’t scale as well as digital, these blocks may represent a substantial portion of the SoC.
On top of that, many so-called analog blocks now have digital control logic, turning more “analog” IP into mixed-signal form. Thus, as SoC capacity continues to rapidly expand, a single IP block may represent an extremely complex mixed-signal function.
Burgeoning demand for mixed-signal SoC integration creates new challenges in both physical implementation and verification. For example, analog and digital designers utilize different implementation tools and flows, with little communication between teams.
Analog/mixed-signal IP blocks are typically “black boxes” with fixed pinouts and no visibility into internal layouts. Digital designers struggle to integrate these macros into the SoC’s floorplan, which frequently requires iterations between digital and analog designers. Meanwhile, digital switching can cause noise and signal-integrity problems for analog circuits, often requiring extra shielding.
Mixed-signal verification is an extremely difficult challenge for SoC integrators. Analog IP blocks are presumably pre-verified with a Spice simulator, but they still must be verified in the context of the SoC. Traditional analog simulation is far too slow, and traditional digital simulation too inaccurate, to fully verify and debug analog/digital interfaces.
Top-level, mixed-signal SoC verification is also difficult because it encompasses both analog and digital IP blocks at different levels of abstraction. The blocks could be represented in schematics, Spice netlists, analog behavioral models, or purely digital models.
According to industry estimates, more than 50% of SoC design respins at 65 nm and below are due to mixed-signal errors. A respin may cost an extra $5 million to $10 million and cause up to a six- to eight-week delay in a product rollout, with potentially disastrous consequences.
Many respins are due to commonplace, avoidable errors like inverted or disconnected signals. To avoid these errors, mixed-signal SoC teams need to implement verification methodologies that can quickly and accurately validate interfaces between analog and digital domains.
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Interoperable Implementation Flows Needed
Today’s physical implementation methodologies are generally either “netlist-driven” flows from a digital cockpit or “schematic-driven” flows from an analog cockpit. In both cases, these flows were developed to deal with relatively simple integration challenges.
In schematic-driven flows, a custom design environment such as the Cadence Virtuoso Layout Suite platform handles the floorplanning, chip assembly, and block integration. Digital blocks are custom designed or imported from a digital design environment such as the Cadence Encounter Digital Implementation system.
Netlist-driven (Verilog/VHDL) flows handle the floorplanning, chip assembly, and block integration in a digital design system. Hardened analog IP blocks are imported from an analog/custom design environment like the Virtuoso Layout Suite.
While these methodologies will remain important, SoC designers need a new approach as the amount of complex mixed-signal content grows, and as analog and digital circuits become more functionally coupled. This new approach will allow concurrent design of analog and digital blocks, and feature flexible pin assignments to enable placement within a true mixed-signal floorplan.
While analog and digital designers will still retain their own familiar design environments, a common database representation will simplify the integration of analog, digital, and mixed-signal blocks. Responsibility for chip assembly and tapeout will be shared. In short, no hard separation will exist between “analog” and “digital” design.
One big advance with this new approach is that analog and digital blocks can be designed concurrently. Floorplanning can be truly mixed-signal, with flexibility to assign or optimize pins. Results can include earlier floorplanning, smaller area, less routing congestion, earlier chip finishing, and faster overall turnaround times.
Let’s take a look at a representation of an advanced mixed-signal implementation flow (Fig. 1). In the diagram, the left shaded portions represent tasks undertaken in the analog environment, while the right shaded portions represent tasks performed by digital designers.
Notice that the top-level floorplan becomes a joint exercise between analog and digital design groups. These teams concurrently optimize the floorplan, changing pinouts and locations and routing nets as needed, until they can both sign off on the floorplan.
Once the floorplan is completed, custom and digital block implementation follow in separate analog and digital environments. Some blocks may also be imported as pre-existing or purchased IP. Top-level implementation, like floorplanning, becomes a shared exercise between analog and digital teams, with necessary readjustments made on either side. Chip assembly and analysis are also shared.
The Cadence Virtuoso and Encounter platforms support the aforementioned flow. The fast data transfers enabled by the shared OpenAccess database greatly facilitate this flow. Instead of slow, incomplete Library Exchange Format/Data Exchange Format (LEF/DEF) transfers of black boxes, analog and digital designers can quickly view and manipulate analog and digital blocks. But analog designers can still “lock” features such as guard rings to protect them from unwanted editing.
Retaining Design Intent Can Prevent Noise Problems
Placement of analog blocks is important to avoid signal-integrity problems and to allow sufficient routing resources. Special care must be taken to properly place sensitive analog blocks that can be impacted by digital switching noise.
In addition to shielding, analog blocks may have to meet specific area or aspect-ratio requirements. A mixed-signal routing capability that manages analog constraints (e.g., shielding, matching, differential pairs, and bus routing) while still providing high-speed digital routing is an important part of an integrated mixed-signal implementation flow.
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Mixed-signal designs raise the risk of chip malfunction due to coupling through the substrate. One way or another, designers must predict and minimize substrate noise. For example, full-chip substrate analysis can help designers determine where guard rings are required and whether spacing is sufficient to avoid substrate noise. The analysis should identify digital noise sources caused by simultaneous switching, model noise transmission through the substrate, and report the impact of digital noise on sensitive analog components.
Timing Verification Challenges
The verification of digital timing paths inside mixed-signal blocks is problematic in traditional netlist-driven flows. Typically, digital implementation tools extract path parasitics only to the analog IP block’s instance pin. A .lib file models any loading inside the block (Fig. 2, left). Generating that .lib file can turn into a painful experience for analog designers.
The Encounter Digital Implementation system offers another approach, which involves the extraction of full-path parasitics all the way to the digital instance pin (Fig. 2, right). The tool models the loading of the digital path inside a mixed-signal block as a distributed RC network. Internal loading is thus appended to the extracted path, and static timing analysis can verify the complete path with no need to generate a .lib file.
Use Abstraction To Improve Verification Efficiency
Mixed-signal SoC verification involves many different levels of abstraction. In general, transistor-level simulation with Spice remains the gold standard for analog IP verification. While it provides very high accuracy, Spice is much too slow for chip-level simulations unless it’s used extremely selectively.
To achieve reasonable simulation speeds, many mixed-signal teams employ analog behavioral modeling. This approach can be five to 100 times faster than Spice. The actual speedup varies widely depending on the application and the level of detail in the model. Analog behavioral models are typically written in one of the following languages:
• Verilog-AMS: a mixed-signal modeling language based on IEEE-1364 Verilog that can define both analog and digital behavior, offering both continuous-time and event-driven modeling semantics
• Verilog-A: the continuous-time subset of Verilog-AMS, aimed at analog design
• VHDL-AMS: similar in concept to Verilog-AMS, this language provides analog and mixed-signal extensions to IEEE-1076 VHDL
It’s helpful to examine the comparative accuracy and simulation performance between Spice, FastSpice, analog behavioral modeling (with Verilog-AMS and VHDL-AMS), and pure digital simulation (Fig. 3). The chart also includes real number modeling (RNM) with the “real” and “wreal” data types, which make it possible to represent analog signal values in digital simulations.
Performance numbers are generic and can vary significantly for different applications. Note the potentially wide range of accuracy and performance for Verilog-AMS and VHDL-AMS behavioral models.
Another important factor is the effort required to set up a simulation and create the model (Fig. 4). While Spice simulations run slowly, they’re relatively easy to set up. The time required to create a high-quality analog behavioral model, however, can range from hours to days, or even weeks.
RNM is restricted to a signal-flow approach, it doesn’t require analog convergence, and there’s no new language to learn. Consequently, the real/wreal modeling effort is less than that for Verilog-AMS or VHDL-AMS.
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Co-simulation and RNM
Co-simulation between analog and digital solvers is one methodology for mixed-signal block and chip verification. However, several limitations plague traditional co-simulation approaches.
For example, early co-simulation environments typically employed Verilog and Spice operating in separate simulation kernels linked through interprocess communications (IPC). This made it difficult to keep analog and digital simulation engines in lockstep. Users often had to partition the circuit, deal with two netlists, and cope with two disparate debugging environments.
A better approach is to use a single, executable kernel for both analog and digital simulation engines. The Cadence Virtuoso AMS Designer Simulator takes that approach by linking the Virtuoso design platform with the Cadence Incisive digital verification platform. Virtuoso AMS Designer supports analog behavioral models, transistor-level circuit models, and digital simulation models.
Abstract Analog Blocks For SoC Verification
Another new approach to mixed-signal verification is the previously noted real number modeling, which is supported in both the Virtuoso and Incisive platforms (Fig. 3, again). This allows the simulation of discrete, floating-point real numbers that can represent voltage levels. With RNM, users can describe an analog block as a signal flow model and then simulate it in a digital solver at near-digital simulation speeds.
For analog and mixed-signal block verification, RNM can accelerate high-frequency portions of the analog signal path, which take the longest to verify in simulation, while dc bias and low-frequency portions remain in Spice. But the greatest advantage of RNM lies in top-level SoC verification, where engineers can represent all electrical signals as RNM equivalents and stay entirely within the digital simulation environment.
The most obvious advantage of using RNM for top-level SoC verification is that it runs nearly as fast as pure digital simulation. It runs orders of magnitude faster than Spice-based simulation or even analog behavioral modeling. Thus, full-chip verification becomes possible for large mixed-signal SoCs, and it allows for nightly, high-volume regression tests.
Another advantage of staying within the digital simulation environment is the availability of a metric-driven verification (MDV) methodology. In the Incisive verification environment, MDV makes it possible to create verification plans, measure progress, and more easily determine when the verification process is complete. Functional and code coverage, checks, and assertions provide the verification metrics used to determine closure.
With the march toward advanced process nodes and the emergence of extremely complex analog/mixed-signal IP blocks, mixed-signal SoC integration has become a daunting task. Fortunately, there are solutions.
A new implementation flow promises concurrent analog/digital IP design and integration. Advanced techniques help to resolve noise and timing verification challenges. Techniques such as analog behavioral modeling, single-kernel analog/digital simulation, and real number modeling are opening doors to mixed-signal SoC verification. All of these approaches are part of the EDA360 vision and are needed to turn silicon realization of mixed-signal SoCs into a reality.