RISC-V RVA23—A Major Milestone

What you'll learn:

• The RVA23 and its features.
• What about RISC-V fragmentation?
• RISC-V Profiles and options.
• What the future holds for RISC-V.

The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of RISC-V, positioning it as a strong contender for application processor dominance.

RVA Profiles align implementations of RISC-V 64-bit application processors that will run rich operating systems (OS) stacks from standard binary OS distributions. They’re essential to software portability across many hardware implementations and help to avoid vendor lock-in.

The RISC-V instruction set architecture (ISA) was designed to provide a highly modular and extensible instruction set. It includes a large and growing set of standard extensions, where each standard extension is a bundle of instruction-set features. This is no different than other industry ISAs that continue to add new ISA features.

Unlike other ISAs, though, RISC-V has a broad set of contributors and implementers, and it allows users to add their own custom extensions. For some deep embedded markets, highly customized processor configurations are desirable for efficiency, and all software is compiled, ported, and/or developed in-house by the same organization for that specific processor configuration. However, other markets that expect a substantial fraction of software to be delivered to end-customers in binary form requires compatibility across multiple implementations from different RISC-V vendors.

In embedded applications, developers may have a vertically integrated software approach controlling the entire vertical software stack, leading to what some may call a "spaghetti code" way of working. Still, modern application processors from different vendors need to run the same binary OS distribution without changes. If an OS vendor targets just the minimal compatibility across products to produce a distribution that fits all, it would be slightly more than the very basic RV64G only, which is a subset that’s too small.

RVA23: A New Era for RISC-V

RVA23 is the second major release of the application processor Profile. It builds on the foundation established by RVA20. This Profile introduces crucial mandatory features such as:

• Vectors: The Vector extension accelerates math-intensive workloads, including AI/ML, cryptography, and compression/decompression. Vector extensions yield better performance in mobile and computing applications with RVA23 as the baseline requirement for the Android RISC-V ABI.
• Hypervisor: The Hypervisor extension will enable virtualization for enterprise workloads in both on-premises server and cloud-computing applications. This will accelerate the development of RISC-V-based enterprise hardware, operating systems, and software workloads. The Hypervisor extension will also provide better security for mobile applications by separating secure and non-secure components.

While the vector extension was optional in RVA22, it’s now mandatory in RVA23. We want hardware and software developers to use vector and vector crypto, since they’re much faster than scalar operations. As a result, the vector V extension that was an option in RVA22U64 is now mandatory, and new Zvkng and Zvksg are introduced as options for vector crypto.

With the RVA23 Profile, developers can benefit from flexible vector instructions that support multiple data formats, are future-proof thanks to being variable-length, reduce code size, and enable significant acceleration in performance.

RISC-V is also standardizing C intrinsic APIs for RVV 1.0 to allow for simplified integration of vector operations in math libraries targeting AI/ML, image processing, and other scientific computations.

Developers can leverage localized vector crypto options to support National Institute of Standards and Technology (NIST) and/or ShangMi algorithms with Galois/Counter Mode (GCM). These options enable developers to customize their implementations, while also helping to streamline software development.

We’re also making the Hypervisor extension mandatory due to the growing demand for secure, efficient virtualization across a wide variety of applications. By mandating the vector and hypervisor features, RVA23 ensures that future RISC-V application processors will have a consistent and powerful feature set, facilitating software development and deployment.

Addressing Fragmentation Concerns

While there may be talk of RISC-V fragmentation due to its modular nature, this isn’t the case. The RVA23 Profile defines a set of mandatory and optional features, ensuring a balance between flexibility and standardization. Such an approach enables hardware vendors to differentiate their offerings while maintaining compatibility with a common software ecosystem.

The primary goal of the RVA Profiles is to align processor vendors targeting binary software markets. Therefore, software can rely on the existence of a certain set of ISA features in a particular generation of RISC-V implementations.

Alignment isn’t only for compatibility, but also to ensure RISC-V is competitive in these markets. The binary app markets are generally those with the most competitive performance requirements (e.g., mobile, client, and server).

RISC-V International can’t mandate the ISA features that a RISC-V binary software ecosystem should use. Rather, each ecosystem will typically select the lowest-common denominator among the available deployed devices in their target markets. RISC-V international and the stakeholders of each software ecosystem can collaborate with the hardware vendors on the ISA roadmap and mandate specific extensions and a common set of features through the RVA Profiles that will provide the best performance and security in each generation. 

In addition to the mandatory extensions, OS vendors can support a limited set of additional options that will be discoverable at runtime.

RISC-V Profiles and Options

RISC-V members have been working on Profiles by grouping the most important key extensions together into four lists for a given class of RISC-V application processors: mandatory, localized, development, and expansion.

All ISA extensions agreed upon by RISC-V members as fundamental for a modern high-performing application processor are included in the list of mandatory extensions. They must be implemented in all system-on-chips (SoCs) that vendors want to verify as compliant with a given Profile.

The first kind of non-mandatory options is the list of localized options, whose presence or use necessarily differs along geopolitical and/or jurisdictional boundaries, with crypto being an example. These will always be optional. In the case of crypto, discovery has been found to be perfectly acceptable to handle this optionality in other architectures, as the use of the extensions is well contained in certain libraries.

The second kind of optional extensions is the list of development options. It represents a new ISA extension in an early part of its lifecycle, but which is intended to become mandatory in a later generation of the RVA Profile. Processor vendors and software toolchain providers will have varying development schedules, and providing an optional phase in a new extension’s lifecycle offers some flexibility while maintaining overall alignment. This is particularly appropriate when hardware or software development for the extension is complex. Denoting an extension as a development option signals to the community that development should be prioritized for such extensions, as they will become mandatory.

The third type of optional extensions is the list of expansion options. Such options may have a large implementation cost but aren’t always needed in a particular platform, and they can be readily handled by discovery. These are also intended to remain available as expansion options in future versions of the Profile.

Several supervisor-mode extensions fall into this category, e.g., Sv57, which has a notable PPA impact over Sv48 and isn’t needed on smaller platforms. Some unprivileged extensions that may fall into this category are possible future matrix extensions. These have large implementation costs, and use of matrix instructions can be readily supported with discovery and alternate math libraries.

The Future of RISC-V

The future of RISC-V looks bright, with ongoing efforts to:

• Improve specifications: Streamlining the RISC-V specification documentation for better clarity and consistency.
• Advance AI capabilities: Developing and standardizing matrix extensions and other AI-specific features.
• Enhance security: Strengthening security features to protect RISC-V-based systems from emerging threats.

The RISC-V community is actively shaping the future of computing. With the ratification of RVA23, RISC-V is becoming a significant and growing force in the application processor market. As the ecosystem continues to grow, we can expect to see innovative and powerful RISC-V-based devices emerge across a wide variety of use cases.