Silicon densities, both for ASICs and FPGAs, can now support true systems-on-a-chip (SoCs). This level of design requires busing systems to connect various components, including 1 or more microprocessors, memory, peripherals, and special logic. AMBA, the Advanced Microprocessor Bus Architecture, is ARM's on-chip busing solution. Initially designed to support the ARM processor cores, AMBA is now licensed and deployed for use with other RISC cores. It's one of the leading on-chip busing systems. Competitors of AMBA include IBM's CoreConnect (www.chips.ibm.com) and Silicore's Wishbone (www.silicore.net) bus systems.
The system buses support 32-, 64-, and 128-bit data-bus im-plementations with a 32-bit address bus, as well as smaller byte and half-word designs. These are synchronous, nonmultiplexed buses that support bursting and pipelining, and in the more advanced version, a simple split transaction. The ASB is used for simpler, more cost-effective designs, whereas more sophisticated designs call for the employment of the AHB. Presently, ARM is working to en-hance the AHB for more-effective MP operation.
The AMBA bus system defines a bus hierarchy of a system bus and a peripheral bus. The two buses are linked via a bridge that serves as the master to the peripheral bus slave de-vices. The system bus can be 1 of 2 defined buses: the newer AHB, the Advanced High-Speed Bus, or else the earlier ASB, the Advanced System Bus. The peripheral bus, called APB for the Advanced Peripheral Bus, is a simpler, lower-speed, low-power bus for slower devices.
In a typical configuration, the SoC processor(s), memory controllers, on-chip memory, and DMA controllers hang off of the system bus. It handles the high-speed bus interconnections on the chip. The slower peripherals are hung off of the slower, simpler APB peripheral bus. These also include special logic functions and connections to the SoC basic logic.
The SoC's system and peripheral buses can run at different clock rates. They link via a bridge that buffers data and operations between the two buses. The system buses are different in that AHB isn't a superset of ASB, nor does it build on the same control signals. But the buses do have a lot in common. They're multimaster, they use a central arbiter, each transfer has an address and control cycle, and they're both pipelined (able to start the next transfer's arbitration and address phase while finishing the current transfer).
AHB supports bursts, with 4-, 8-, and 16-beat bursts, as well as undefined-length bursts and single transfers. Bursts can be address wrapped, i.e., staying within a fixed address range. Bursts can't cross a 1-kB address boundary, though. Slaves can insert wait states to adjust its response (up to 16).
All bus operations are initiated by bus masters, which also can serve as a slave. The master-generated address is decoded by a central address decoder that provides a select signal to the addressed bus slave unit. The bus master can "lock" the bus, reserving it with the central arbiter for a series of locked transfers.
The slave unit has the option to terminate a transaction as an error, signal the master to retry, or split the transaction for later completion. Split transactions enable the slave to defer the operation until it's able to accomplish it, thereby releasing the bus for other accesses. The slave signals a split transaction and saves the master number (HMASTER\\[\\]). When ready to complete the transaction, the slave signals the arbiter with the master number. When the arbiter grants bus access to the master, it restarts the transaction. No master can have more then 1 pending split transaction.
For every bus data transfer, the slave must respond, telling the master to continue (WAIT), that the transfer is done (DONE), that the transfer has resulted in an error condition (ERROR), that the slave can't accept any more transfers (LAST), or that the transfer should be retried (RETRACT). The WAIT, DONE, ERROR, LAST, and RETRACT signals are generated on the next cycle by the slave bus unit.
ASB is a nonmultiplexed bus with a single data bus (BD\\[\\]). The BWRITE signal indicates the transfer direction (read or write), and BSIZE\\[\\] specifies the transfer size (width). The slaves don't have to check the bus addresses to see if they're being addressed. Instead, the bus address is used to generate a select signal (DSELx) to select the addressed slave bus unit.
As a simple bus, the APB doesn't support bursting. Each transaction consists of 2 cycles: an address cycle (Setup state) and a data cycle (Enable state). The bus uses a single clock, PCLK. In Setup, the bus brings PSEL and PWRITE up, putting the address on the PADDR address bus. In the Enable state, it brings PENABLE up and places data on the PWDATA/PRDATA bus. The enable signal, PENABLE, is deasserted on the next clock.
|AMBA ADVANCED HIGH-SPEED BUS|
|AMBA ADVANCED SYSTEM BUS|
|AMBA ADVANCED PERIPHERAL BUS|