RISC-V Core Exceeds RVA23 Requirements

The RISC-V RVA23 is a 64-bit specification that requires vector and hypervisor support with cache coherency. These were optional with RVA22. RVA23 is the base for Linux distributions like Ubuntu 25.10. Vector extensions can be exploited to support artificial-intelligence (AI) models.

SiFive’s P570 builds on the RVA23 specification, adding features like WorldGuard security support that provides features similar to Arm’s TrustZone. It can be utilized in a multicore cluster with multiple clusters as needed (Fig. 1). Each core is built on a 3-wide, 13-stage, fully out-of-order execution superscalar pipeline architecture. The 128-bit vector pipeline includes dot product extensions.

The cores support FP16 and BF16 floating-point formats that are often employed in artificial-intelligence/machine-learning (AI/ML) models.

Compared to its predecessor, the P550, the P570 provides a 13% improvement in dynamic power along with a 51% reduction in leakage current. It delivers twice the vector performance as well.

The P570, implementing SiFive’s third-generation architecture, is part of SiFive’s family of RISC-V cores (Fig. 2), including the high-end P870 that’s often paired with the X390 neural processing unit (NPU). The P870 targets the high end while the P570 hits the midrange, where a smaller footprint is useful.

The P570 includes a number of enhancements, primarily to augment vector operations (see table below). These work with the 128-bit vector pipeline. Others, like smepmp, improve security, which involves vector cryptography support, secure branch prediction, and support for protected memory.

Having vector and hypervisor features, along with additional security and vector optimizations, will prove useful in embedded applications that require some AI/ML in addition to regular computational support. The P550 is still available if an application doesn’t need some of the more advanced features found in the P570.