Checking Out the RISC-V Summit North America 2025
Though the RISC-V Summit North America is over, you can peruse the videos of most of the keynotes and sessions here. The list is quite long, so we picked a few and included them in this space, such as Understanding the RISC-V Extensions for AI with John Simpson, the Senior Principal Architect at SiFive (watch the video above).
I chose a few videos to embed here along with a list of additional selections after that.
Embedded Videos
- Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
- Utilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling
- Enhancing RISC-V Embedded Processor Performance Through Advanced Instruction Fusion
- Next-Generation Edge AI with RISC-V Vector Cores for Vision Applications
More RISC-V Content on Electronic Design
Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
Rich Fuhler, Technical Director at Andes Technology, talks about scalar SIMD DSP (Single Instruction, Multiple Data Digital Signal Processing) instructions and how they fit with RISC-V (watch the video below). SIMD is handy for artificial-intelligence (AI) applications as well.
Andes provides RISC-V cores and development tools.
Utilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling
The RISC-V Foundation has adopted debugging and tracing standards, including the RISC-V E-Trace Standard and the RISC-V N-Trace Standard that are applicable for heterogeneous systems. Dennis Griffith, a Field Application Engineer with Lauterbach, presents the standards and how to take advantage of them (watch the video below).
Enhancing RISC-V Embedded Processor Performance Through Advanced Instruction Fusion
Carlos Basto and Revi Ofir from Synopsys present a novel mechanism for fusing common pairs of RISC-V instructions,. It's aimed at improving processor pipeline efficiency, particularly for resource-constrained embedded processors (watch the video below).
Next-Generation Edge AI with RISC-V Vector Cores for Vision Applications
Florian Zaruba, Principal Engineer at Axelera AI, shows how RISC-V vector cores can enhance vision systems by providing more efficient vision pipelines.
More Videos from the North America RISC-V Summit
You can watch these videos on YouTube:
- AI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at Scale - Watch how proteanTecs’ deep data IP monitoring system works with Andes’ AX45MPV vector processor
- Extending the RISC-V Open Source Ecosystem - Darshak Koshiya, Senior Principal Engineer with Tenstorrent, talks about the open-source ecosystem for RISC-V.
- Moving to RISC-V Vector: A Practical Journey of AI Operator Optimization - What's the difference between the Arm scalable vector extensions (SVE) and RISC-V Vector 1.0 standards? RISCstar Solutions' Guodong Xu provides the answer in this video.
- CVA6-CHERI - An Open-source RV64Y Implementation for Commercialization - Capability Hardware Enhanced RISC Instructions (CHERI) is a memory security system that's processor-agnostic, and it can be implemented as part of a RISC-V core. Jonathan Woodruff and Alexandre Joannou from Capabilities Limited present the open-source RV64Y CHERI implementation.
- The RISE Project: Advancing RISC-V Software - The Linux Foundation's RISC-V Software Ecosystem (RISE) Project is an industry collaborative effort to accelerate RISC-V software development. Rivos' Ludovic Henry and Google's Nathan Egge highlight RISE.
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William G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
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