USB 2.0 Chips Simplify Design Of High-Speed Serial Interfaces

Oct. 2, 2000
USB 2.0 is poised to make a big splash and break USB 1.1's 12-Mbit/s bottleneck. With a maximum bandwidth of 480 Mbits/s, the USS-2200 host controller chip supports both specifications by incorporating both controllers in a single...

USB 2.0 is poised to make a big splash and break USB 1.1's 12-Mbit/s bottleneck. With a maximum bandwidth of 480 Mbits/s, the USS-2200 host controller chip supports both specifications by incorporating both controllers in a single chip.

Produced by Lucent Technologies, the USS-2200 includes the company's USB 1.1 QuadraBus design. This feature doubles USB 1.1 performance by using four complete USB 1.1 OHCI Host Core ports per chip instead of multiplexing four ports. The same set of cores can be found in Lucent's USB 1.1 chip set.

The USB 2.0 support incorporates its own PCI interface along with a list processor module and pipeline/cache control module. The serial interface engine multiplexes signals with each PHY. Also, there is a PHY for each of four channels. These channels are shared by the USB 2.0 and USB 1.1 interfaces. The USB 2.0 protocol supports USB 1.x peripherals. But in Lucent's implementation, different portions of the chip handle each peripheral.

Chips like the USS-2200 will significantly improve the performance of external DVD and hard disks, high-resolution printers, digital video cameras, high-resolution scanners, DSL and cable modems, and other applications. Shrinking support to a single chip reduces board size and cost while improving reliability and power consumption.

Contact the company for pricing and availability information.

Lucent Technologies, 600 Mountain Ave., Murray Hill, NJ 07974; (908) 582-8500; www.lucent.com.

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William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

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